# US 2019/0174631 A1 · Miniaturized circuit and method of making the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0174631 A1
- Document ID: US20190174631A1
- Status: Published application
- Kind: A1
- Application number: 16/156,920
- Filed: 2018-10-10
- Published: 2019-06-06
- Earliest claimed: 2017-12-04
- Assignees: Siward Crystal Technology Co., Ltd.
- Applicants: Siward Crystal Technology Co., Ltd.
- Inventors: Yen-Hao TSENG; Shih-Ying HUANG; Yu-Hsuan PENG; Wei-Chih HSU; Wei-Lin WANG; Wen-Kuan HUANG
- Web page: https://patentgrep.com/patent/US20190174631A1

## CPC

- H05K 3/067: {Etchants}
- H05K 3/064: {Photoresists}
- H05K 3/108: {by semi-additive methods; masks therefor (characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241)}
- H05K 3/4661: {Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor (other insulating materials H05K3/387)}
- H05K 1/09: Use of materials for the {conductive, e.g. } metallic pattern
- H05K 2201/0347: Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
- H05K 2203/0723: Electroplating, e.g. finish plating
- H05K 2203/0786: Using an aqueous solution, e.g. for cleaning or during drilling of holes
- H05K 2203/125: Inorganic compounds, e.g. silver salt
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

A method for making a miniaturized circuit includes: depositing a bottom metal layer including a first metal on a substrate; forming a patterned photoresist layer on the bottom metal layer to expose a first portion of the bottom metal layer and to cover a second portion thereof; plating a middle circuit pattern including a second metal on the bottom metal layer to cover the first portion of the bottom metal layer; plating a top circuit pattern including a third metal different from the first metal onto the middle circuit pattern to cover the middle circuit pattern; removing the patterned photoresist layer; and etching the second portion of the bottom metal layer with an etchant, so as to pattern the bottom metal layer into a bottom circuit pattern.

## Claims

### Claim 1

A method for making a miniaturized circuit, comprising the steps of:
depositing a bottom metal layer on a surface of a substrate, the bottom metal layer including a first metal;
forming a patterned photoresist layer on the bottom metal layer such that a first portion of the bottom metal layer is exposed from the patterned photoresist layer and a second portion of the bottom metal layer is covered by the patterned photoresist layer;
plating a middle circuit pattern on the bottom metal layer so that the first portion of the bottom metal layer is covered by the middle circuit pattern, the middle circuit pattern including a second metal;
plating a top circuit pattern onto the middle circuit pattern so as to cover a portion of the middle circuit pattern that is not in contact with the bottom metal layer and the patterned photoresist layer, the top circuit pattern including a third metal different from the first metal;
removing the patterned photoresist layer to expose the second portion of the bottom metal layer; and
etching the second portion of the bottom metal layer with an etchant, so as to pattern the bottom metal layer into a bottom circuit pattern, the bottom circuit pattern being disposed underneath the middle circuit pattern.

### Claim 2 (depends on 1)

The method of claim 1, wherein the etchant etches the first metal at a first rate R1 and etches the third metal at a second rate R2, R1 being higher than R2.

### Claim 3 (depends on 2)

The method of claim 2, wherein the ratio of R1 to R2 is not lower than 100.

### Claim 4 (depends on 2)

The method of claim 2, wherein the first and second metals are independently selected from the group consisting of Cu, Au and the combination thereof, and the third metal is Ni.

### Claim 5 (depends on 4)

The method of claim 4, wherein the etchant is an aqueous solution including ceric ammonium nitrate.

### Claim 6 (depends on 5)

The method of claim 5, wherein each of the first and second metals is Cu, and the concentration of ceric ammonium nitrate in the aqueous solution ranges from 5 wt % to 10 wt %.

### Claim 7 (depends on 1)

The method of claim 1, wherein the bottom circuit pattern has a thickness t0, and the middle circuit pattern has a thickness t1, t0 being smaller than t1.

### Claim 8 (depends on 1)

The method of claim 1, wherein t0 ranges from 100 nm to 200 nm, and t1 ranges from 5 μm to 15 μm.

### Claim 9

A miniaturized circuit comprising:
a substrate;
a bottom circuit pattern that is formed on a surface of said substrate and that includes a first metal;
a middle circuit pattern that is deposited on said bottom circuit pattern and that includes a second metal; and
a top circuit pattern that is deposited on said middle circuit pattern and covers a portion of the middle circuit pattern that is not in contact with the bottom circuit pattern, and that includes a third metal different from said first metal.

### Claim 10 (depends on 9)

The miniaturized circuit of claim 9, wherein said first and second metals are independently selected from the group consisting of Cu, Au and the combination thereof, and said third metal is Ni.

### Claim 11 (depends on 9)

The miniaturized circuit of claim 9, wherein said bottom circuit pattern has a thickness t0, and said middle circuit pattern has a thickness t1, t0 being smaller than t1.

### Claim 12 (depends on 11)

The miniaturized circuit of claim 11, wherein t0 ranges from 100 nm to 200 nm, and t1 ranges from 5 μm to 15 μm.