# US 2019/0174146 A1 · Signal-processing apparatus including a second processor that, after receiving an instruction from a first processor, independantly controls a second data processing unit without further instruction from the first processor

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- Number: US 2019/0174146 A1
- Document ID: US20190174146A1
- Status: Published application
- Kind: A1
- Application number: 16/257,317
- Filed: 2019-01-25
- Published: 2019-06-06
- Earliest claimed: 2003-08-21
- Assignees: Socionext Inc.
- Applicants: Socionext Inc.
- Inventors: Tomonori KATAOKA; Hideshi NISHIDA; Kouzou KIMURA; Nobuo HIGAKI; Tokuzo KIYOHARA
- Web page: https://patentgrep.com/patent/US20190174146A1

## CPC

- H04N 19/86: involving reduction of coding artifacts, e.g. of blockiness
- G06F 9/3877: {using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12)}
- G06F 9/3885: {using a plurality of independent parallel functional units}
- H04N 19/42: characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation (H04N19/635 takes precedence)
- H04N 19/436: using parallelised computational arrangements
- H04N 19/44: Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
- H04N 19/523: with sub-pixel accuracy
- H04N 19/61: in combination with predictive coding
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A signal-processing apparatus includes an instruction-parallel processor, a first data-parallel processor, a second data-parallel processor, and a motion detection unit, a de-blocking filtering unit and a variable-length coding/decoding unit which are dedicated hardware. With this structure, during signal processing of an image compression and decompression algorithm needing a large amount of processing, the load is distributed between software and hardware, so that the signal-processing apparatus can realize high processing capability and flexibility.

## Claims

### Claim at position 1

1-4. (canceled)

### Claim 5

A signal-processing apparatus comprising:
a first processor;
a second processor controlled directly by the first processor;
a data processing unit controlled directly by the second processor;
a first bus coupled to the data processing unit;
a shared memory coupled to the first bus and used by the data processing unit;
a video input/output unit coupled to the first bus;
a second bus coupled to the first processor; and
a bridge unit coupled to the first bus and the second bus,
wherein the data processing unit comprises at least:
a first hardware block dedicated to deblocking filtering; and
a second hardware block dedicated to motion estimation, and
performs video encode processings on data received from the video input/output unit or performs video decode processings to generate data to be output through the video input/output unit.