# US 2019/0174084 A1 · Image sensor capable of averaging pixel data > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0174084 A1 - Document ID: US20190174084A1 - Status: Published application - Kind: A1 - Application number: 15/830,754 - Filed: 2017-12-04 - Published: 2019-06-06 - Earliest claimed: 2017-12-04 - Assignees: Pixart Imaging Inc. - Applicants: PixArt Imaging Inc. - Inventors: Chia-Chi KUO; Jui-Te CHIU; Han-Chi LIU; Peng-Sheng CHEN; Yi-Cheng CHIU - Web page: https://patentgrep.com/patent/US20190174084A1 ## CPC - H04N 25/709: Circuitry for control of the power supply - H04N 25/42: by switching between different modes of operation using different resolutions or aspect ratios, e.g. switching between interlaced and non-interlaced mode - H04N 25/46: by combining or binning pixels - H04N 25/76: Addressed sensors, e.g. MOS or CMOS sensors - H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters - H04N 25/706: Pixels for exposure or ambient light measuring - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract An image sensor including a first pixel circuit, a second pixel circuit, a first readout line, a second readout line, a first readout circuit, a second readout circuit and an average switch is provided. The first and second pixel circuits are in two columns of a pixel array. The first readout line transmits pixel data of the first pixel circuit to the first readout circuit. The second readout line transmits pixel data of the second pixel circuit to the second readout circuit. The average switch is arranged between the first and second readout lines and used to electrically connect the first and second readout lines in an average mode to average the pixel data on the first and second readout lines. ## Claims ### Claim 1 An image sensor, comprising: a pixel array comprising a first pixel circuit and a second pixel circuit arranged in two columns of a plurality of pixel circuit columns of the pixel array; a first readout line configured to output pixel data of the first pixel circuit; a first readout circuit configured to read the pixel data of the first pixel circuit via the first readout line; a second readout line configured to output pixel data of the second pixel circuit; a second readout circuit configured to read the pixel data of the second pixel circuit via the second readout line; and at least one average switch coupled between the first readout line and the second readout line, wherein in a first mode, the at least one average switch is not conducted, and the first readout circuit and the second readout circuit are turned on, and in a second mode, the at least one average switch is conducted to average the pixel data on the first and second readout lines, and the second readout circuit is turned off. ### Claim 2 (depends on 1) The image sensor as claimed in claim 1, further comprising: a first constant current source coupled between the first readout line and ground; and a second constant current source coupled between the second readout line and the ground, wherein the second constant current source is turned off in the second mode. ### Claim 3 (depends on 1) The image sensor as claimed in claim 1, further comprising at least one row average switch configured to electrically connect, in the second mode, two rows of a plurality of pixel circuit rows of the pixel array to average pixel data of the two pixel circuit rows. ### Claim 4 (depends on 1) The image sensor as claimed in claim 1, wherein pixel circuits in every row of the two columns of the plurality of pixel circuit columns are electrically connected, in the second mode, via the at least one average switch to average pixel data of the pixel circuits in every row of the two pixel circuit columns. ### Claim 5 (depends on 1) The image sensor as claimed in claim 1, wherein the first readout circuit includes a correlated double sampling circuit connected to the first readout line, and the second readout circuit includes a correlated double sampling circuit connected to the second readout line. ### Claim 6 (depends on 1) The image sensor as claimed in claim 1, wherein the first readout circuit and the second readout circuit respectively comprise a column analog-to-digital converter (CADC) connected to the first readout line and the second readout line, the CADC comprises a comparator and a detected signal sample capacitor coupled to one input terminal of the comparator, and the at least one average switch is connected between the detected signal sample capacitor and the associated pixel circuit. ### Claim 7 (depends on 6) The image sensor as claimed in claim 6, wherein another input terminal of the comparator is configured to receive a ramp voltage. ### Claim 8 An image sensor, comprising: a pixel array comprising a first pixel circuit and a second pixel circuit arranged in two columns of a plurality of pixel circuit columns of the pixel array; a first readout line configured to output pixel data of the first pixel circuit; a first column analog-to-digital converter (CADC) comprising a first comparator, a first detected signal sample capacitor coupled to one input terminal of the first comparator, and a first reference signal sample capacitor coupled to another input terminal of the first comparator; a second readout line configured to output pixel data of the second pixel circuit; a second CADC comprising a second comparator, a second detected signal sample capacitor coupled to one input terminal of the second comparator, and a second reference signal sample capacitor coupled to another input terminal of the second comparator; a first average switch coupled between the one input terminal of the first comparator and the one input terminal of the second comparator; and a second average switch coupled between the another input terminal of the first comparator and the another input terminal of the second comparator, wherein in a first mode, the first average switch and the second average switch are not conducted, and the first CADC and the second CADC are turned on, and in a second mode, the first average switch and the second average switch are conducted to average the pixel data on the first readout line and the second readout line, and the second CADC is turned off. ### Claim 9 (depends on 8) The image sensor as claimed in claim 8, further comprising: a first constant current source coupled between the first readout line and ground; and a second constant current source coupled between the second readout line and the ground, wherein the second constant current source is not turned off in the second mode. ### Claim 10 (depends on 8) The image sensor as claimed in claim 8, wherein a first end of the first average switch is connected between the first detected signal sample capacitor and the one input terminal of the first comparator, and a second end thereof is connected between the second detected signal sample capacitor and the one input terminal of the second comparator, and a first end of the second average switch is connected between the first reference signal sample capacitor and the another input terminal of the first comparator, and a second end thereof is connected between the second reference signal sample capacitor and the another input terminal of the second comparator. ### Claim 11 (depends on 8) The image sensor as claimed in claim 8, further comprising a reference signal generator configured to generate a ramp voltage signal to the first and second reference signal sample capacitors. ### Claim 12 (depends on 8) The image sensor as claimed in claim 8, wherein pixel data of pixel circuits in every row of the two columns of the plurality of pixel circuit columns are averaged, in the second mode, via the first and second average switches. ### Claim 13 An image sensor, comprising: a pixel array comprising a first pixel circuit and a second pixel circuit arranged in two columns of a plurality of pixel circuit columns of the pixel array; a first readout line configured to output pixel data of the first pixel circuit; a first column analog-to-digital converter (CADC); a second readout line configured to output pixel data of the second pixel circuit; a second CADC; a first storing circuit coupled between the first readout line and the first CADC, and configured to store the pixel data of the first pixel circuit; a second storing circuit coupled between the second readout line and the second CADC, and configured to store the pixel data of the second pixel circuit; a first bypass path configured to bypass the first storing circuit; a second bypass path configured to bypass the second storing circuit; and at least one average switch coupled between the first storing circuit and the second storing circuit, wherein in a first mode, the at least one average switch is not conducted and the first and second bypass paths are conducted, the first CADC is configured to convert the pixel data of the first pixel circuit to digital data, and the second CADC is configured to convert the pixel data of the second pixel circuit to digital data, and in a second mode, the at least one average switch is conducted to average the pixel data of the first storing circuit and the second storing circuit, the first and second bypass paths are not conducted and the second CADC is turned off. ### Claim 14 (depends on 13) The image sensor as claimed in claim 13, further comprising: a first voltage buffer coupled between the first storing circuit and the first CADC; and a second voltage buffer coupled between the second storing circuit and the second CADC. ### Claim 15 (depends on 13) The image sensor as claimed in claim 13, wherein the first storing circuit comprises a first storage capacitor configured to store the pixel data of the first pixel circuit, and a first sample switch coupled to a first end of the first storage capacitor and configured to control the pixel data of the first pixel circuit to be stored into the first storage capacitor, and the second storing circuit comprises a second storage capacitor configured to store the pixel data of the second pixel circuit, and a second sample switch coupled to a first end of the second storage capacitor and configured to control the pixel data of the second pixel circuit to be stored into the second storage capacitor. ### Claim 16 (depends on 15) The image sensor as claimed in claim 15, wherein, in the second mode, the first sample switch and the second sample switch are conducted at first, and then the at least one average switch is conducted after the first sample switch and the second sample switch are opened. ### Claim 17 (depends on 15) The image sensor as claimed in claim 15, further comprising: a first dummy pixel circuit configured to output a first dummy pixel data to a second end of the first storage capacitor; and a second dummy pixel circuit configured to output a second dummy pixel data to a second end of the second storage capacitor. ### Claim 18 (depends on 13) The image sensor as claimed in claim 13, wherein the first CADC and second CADC respectively comprise a comparator and a detected signal sample capacitor coupled to one input terminal of the comparator, and the at least one average switch is connected between the detected signal sample capacitor and the associated pixel circuit. ### Claim 19 (depends on 18) The image sensor as claimed in claim 18, wherein a first end of the first bypass path is connected between the detected signal sample capacitor of the first CADC and the first storing circuit, and a second end thereof is connected between the first storing circuit and the first pixel circuit, and a first end of the second bypass path is connected between the detected signal sample capacitor of the second CADC and the second storing circuit, and a second end thereof is connected between the second storing circuit and the second pixel circuit. ### Claim 20 (depends on 13) The image sensor as claimed in claim 13, wherein the pixel array further comprises a plurality of dummy pixel circuits respectively corresponding to the plurality of pixel circuit columns.