# US 2019/0174083 A1 · Solid-state imaging device

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- Number: US 2019/0174083 A1
- Document ID: US20190174083A1
- Status: Published application
- Kind: A1
- Application number: 16/201,692
- Filed: 2018-11-27
- Published: 2019-06-06
- Earliest claimed: 2002-11-20
- Assignees: Sony Corporation
- Applicants: Sony Corporation
- Inventors: Takashi Abe; Nobuo Nakamura; Tomoyuki Umeda; Keiji Mabuchi; Hiroaki Fujita; Eiichi Funatsu; Hiroki Sato
- Web page: https://patentgrep.com/patent/US20190174083A1

## CPC

- H04N 25/766: comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power
- H04N 25/00: Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N 25/70: SSIS architectures; Circuits associated therewith
- H04N 25/76: Addressed sensors, e.g. MOS or CMOS sensors
- H04N 25/778: comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
- H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
- H04N 25/134: {based on three different wavelength filter elements}
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

A solid-state imaging device is capable of simplifying the pixel structure to reduce the pixel size and capable of suppressing the variation in the characteristics between the pixels when a plurality of output systems is provided. A unit cell includes two pixels. Upper and lower photoelectric converters and, transfer transistors and connected to the upper and lower photoelectric converters, respectively, a reset transistor, and an amplifying transistor form the two pixels. A full-face signal line is connected to the respective drains of the reset transistor and the amplifying transistor. Controlling the full-face signal line, along with transfer signal lines and a reset signal line, to read out signals realizes the simplification of the wiring in the pixel, the reduction of the pixel size, and so on.

## Claims

### Claim at position 1

1-6. (Canceled)

### Claim 7

An imaging device comprising:
a plurality of pixel units, at least one pixel unit of the plurality of pixel units including:
a first photoelectric converter;
a second photoelectric converter;
a first transfer transistor connected to the first photoelectric converter;
a second transfer transistor connected to the second photoelectric converter;
an amplification transistor, wherein a gate of the amplification transistor is connected to the first transfer transistor and the second transfer transistor;
a reset transistor connected to the gate of the amplification transistor;
a selection transistor connected to the amplification transistor;
a voltage supply line connected to a drain of the reset transistor and a drain of the amplification transistor; and
a pixel output line connected to the selection transistor,
wherein the voltage supply line includes a first opening corresponding to a light receiving surface of the first photoelectric converter and a second opening corresponding to a light receiving surface of the second photoelectric converter.

### Claim 8 (depends on 7)

The imaging device according to claim 7, wherein plurality of pixel units are arranged in a matrix of columns and rows, and wherein the first photoelectric converter and the second photoelectric converter are arranged in a column direction.

### Claim 9 (depends on 7)

The imaging device according to claim 7, wherein other pixel units of the plurality of pixels units have a same structure as the at least one pixel unit.

### Claim 10 (depends on 7)

The imaging device according to claim 7, wherein a source of the reset transistor is connected to the gate of the amplification transistor.

### Claim 11

An electronic apparatus comprising:
a signal processing circuit; and
an imaging device including a plurality of pixel units, at least one pixel unit of the plurality of pixel units including:
a first photoelectric converter;
a second photoelectric converter;
a first transfer transistor connected to the first photoelectric converter;
a second transfer transistor connected to the second photoelectric converter;
an amplification transistor, wherein a gate of the amplification transistor is connected to the first transfer transistor and the second transfer transistor;
a reset transistor connected to the gate of the amplification transistor;
a selection transistor connected to the amplification transistor;
a voltage supply line connected to a drain of the reset transistor and a drain of the amplification transistor; and
a pixel output line connected to the selection transistor,
wherein the voltage supply line includes a first opening corresponding to light receiving surfaces of the first photoelectric converter and a second opening corresponding to light receiving surface of the second photoelectric converter.

### Claim 12 (depends on 11)

The electronic apparatus according to claim 11, wherein plurality of pixel units are arranged in a matrix of columns and rows, and wherein the first photoelectric converter and the second photoelectric converter are arranged in a column direction.

### Claim 13 (depends on 11)

The electronic apparatus according to claim 11, wherein other pixel units of the plurality of pixels units have a same structure as the at least one pixel unit.

### Claim 14 (depends on 11)

The electronic apparatus according to claim 11, wherein a source of the reset transistor is connected to the gate of the amplification transistor.