# US 2019/0173734 A1 · Out-of-band management of FPGA bitstreams

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- Number: US 2019/0173734 A1
- Document ID: US20190173734A1
- Status: Published application
- Kind: A1
- Application number: 15/829,935
- Filed: 2017-12-03
- Published: 2019-06-06
- Earliest claimed: 2017-12-03
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Murugasamy K. Nachimuthu; Mohan J. Kumar
- Web page: https://patentgrep.com/patent/US20190173734A1

## CPC

- H04L 41/046: comprising network management agents or mobile agents therefor
- G06F 15/7889: {Reconfigurable logic implemented as a co-processor (instruction execution using a coprocessor G06F9/3877)}
- G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- H04L 9/0894: {Escrow, recovery or storing of secret information, e.g. secret key escrow or cryptographic key storage}
- H04L 41/40: using virtualisation of network functions or resources, e.g. SDN or NFV entities
- G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus}
- G06F 21/76: in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
- H04L 2209/122: Hardware reduction or efficient architectures
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Mechanisms for out-of-band (OOB) management of Field Programmable Gate Array (FPGA) bitstreams and associated methods, apparatus, systems and firmware. Under a first OOB mechanism, a management component, such as a baseband management controller (BMC) is coupled to a processor including an agent in a compute node that includes an FGPA. An FPGA bitstream file is provided to the BMC, and the agent reads the file from the BMC and streams the FPGA bitstream contents in the file to the FPGA to program it. Under second and third OOB mechanisms, a pointer to an FPGA bitstream file that identifies the location of the file that is accessible via a network or fabric is provided to the BMC or other management entity. The BMC/management entity forwards the pointer to BIOS running on the compute node or an agent on the processor. The BIOS or agent then uses the pointer to retrieve the FPGA bitstream file via the network or fabric, as applicable, and streams the FPGA bitstream to the FPGA to program it.

## Claims

### Claim 1

A method performed by a compute node including a processor coupled to a management controller via a first link and to a Field Programmable Gate Array (FPGA) via a second link, the compute node communicatively coupled to at least one of a fabric and a network, the method comprising:
accessing, via an out-of-band (OOB) mechanism, an FPGA bitstream file that is either stored on the compute node or at a location accessible via the fabric or network, the FPGA bitstream file including content comprising an FPGA bitstream; and
programming, via the OOB mechanism, the FPGA by streaming the FPGA bitstream to the FPGA over the second link.

### Claim 2 (depends on 1)

The method of claim 1, wherein the processor further comprises an agent, further comprising:
accessing, via the agent, the FPGA bitstream file; and
writing, via the agent, the FPGA bitstream to the FPGA.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
providing the FPGA bitstream file to the management controller; and
reading, via the agent, the FPGA bitstream file from the management controller.

### Claim 4 (depends on 2)

The method of claim 2, further comprising:
one of providing a pointer to the FPGA bitstream file to the agent or accessing the pointer to the FPGA bitstream file via the agent, the pointer to the FPGA bitstream file identifying a location of the FPGA bitstream file that can be accessed via one of the fabric or network;
retrieving, via the agent, the FPGA bitstream file from the location identified by the pointer, the FPGA bitstream file being retrieved by accessing the network or the fabric; and
streaming the FPGA bitstream to the FPGA to program the FPGA.

### Claim 5 (depends on 1)

The method of claim 1, wherein the processor is further coupled to memory and includes BIOS that is loaded into the memory to be executed by the processor, further comprising:
accessing, via execution of the BIOS, the FPGA bitstream file; and
writing, via execution of the BIOS, the FPGA bitstream to the FPGA.

### Claim 6 (depends on 5)

The method of claim 5, further comprising:
providing the FPGA bitstream file to the management controller; and
reading, via execution of the BIOS, the FPGA bitstream file from the management controller.

### Claim 7 (depends on 5)

The method of claim 5, further comprising:
one of providing a pointer to the FPGA bitstream file to the BIOS via execution of the BIOS or accessing the pointer to the FPGA bitstream file via execution of the BIOS, the pointer to the FPGA bitstream file identifying a location of the FPGA bitstream file that can be accessed via one of the fabric or network;
retrieving, via execution of the BIOS, the FPGA bitstream file from the location identified by the pointer, the FPGA bitstream file being retrieved by accessing the network or the fabric; and
streaming, via execution of the BIOS, the FPGA bitstream to the FPGA to program the FPGA.

### Claim 8 (depends on 1)

The method of claim 1, wherein one of a hypervisor or operating system (OS) virtualization layer is running on the processor, further comprising providing at least one of capabilities and functions associated with the programmed FPGA to the hypervisor or the OS virtualization layer.

### Claim 9 (depends on 8)

The method of claim 8, wherein the at least one of capabilities and functions associated with the programmed FPGA include one or more functions the FGPA is capable of performing that are provided to a hypervisor, further comprising:
exposing the one or more functions to at least one of a virtual machine hosted by the hypervisor or an operating system running on a virtual machine hosted by the processor; and
enabling the operating system to access the FPGA to perform the one or more functions.

### Claim 10 (depends on 8)

The method of claim 8, wherein the at least one of capabilities and functions associated with the programmed FPGA include one or more functions the FGPA is capable of performing that are provided to the OS virtualization layer, further comprising:
exposing the one or more functions to at least one of a container hosted by the OS virtualization layer and an application running in the container; and
enabling the application to access the FPGA to perform the one or more functions.

### Claim 11

An apparatus, comprising:
a processor;
memory, coupled to the processor;
a management controller, communicatively coupled to the processor via a first link;
a Field Programmable Gate Array (FGPA), communicatively coupled to the processor via a second link; and
at least one of a fabric interface and a network interface;
wherein the apparatus is configured to,
access, via an out-of-band (OOB) mechanism, an FPGA bitstream file that is either stored on the compute node or at a location accessible via a fabric or network coupled to the fabric interface or network interface, the FPGA bitstream file including content comprising an FPGA bitstream; and
program, via the OOB mechanism, the FPGA by streaming the FPGA bitstream to the FPGA over the second link.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the processor further comprises an agent, and the apparatus is further configured to:
access, via the agent, the FPGA bitstream file; and
write, via the agent, the FPGA bitstream to the FPGA.

### Claim 13 (depends on 12)

The apparatus of claim 12, further configured to:
receive the FPGA bitstream file at the management controller; and
read, via the agent, the FPGA bitstream file from the management controller.

### Claim 14 (depends on 12)

The apparatus of claim 12, further configured to:
one of providing a pointer to the FPGA bitstream file to the agent or accessing the pointer to the FPGA bitstream file via the agent, the pointer to the FPGA bitstream file identifying a location of the FPGA bitstream file that can be accessed via one of the fabric or network;
retrieving, via the agent, the FPGA bitstream file from the location identified by the pointer, the FPGA bitstream file being retrieved by accessing the network or the fabric; and
streaming the FPGA bitstream to the FPGA to program the FPGA.

### Claim 15 (depends on 11)

The apparatus of claim 11, wherein the processor is further coupled to memory and includes BIOS that is loaded into the memory to be executed by the processor, and the apparatus is further configured to:
access, via execution of the BIOS, the FPGA bitstream file; and
write, via execution of the BIOS, the FPGA bitstream to the FPGA.

### Claim 16 (depends on 15)

The apparatus of claim 15, further configured to:
receive the FPGA bitstream file at the management controller; and
read, via execution of the BIOS, the FPGA bitstream file from the management controller.

### Claim 17 (depends on 15)

The apparatus of claim 15, further configured to:
receive a pointer to the FPGA bitstream file at the management controller, the pointer to the FPGA bitstream file identifying a location of the FPGA bitstream file that can be accessed via one of the fabric or network;
one of provide the pointer to the FPGA bitstream file to the BIOS via execution of the BIOS or access the pointer to the FPGA bitstream file via execution of the BIOS,
retrieve, via execution of the BIOS, the FPGA bitstream file from the location identified by the pointer, the FPGA bitstream file being retrieved by accessing the network or the fabric; and
stream, via execution of the BIOS, the FPGA bitstream to the FPGA to program the FPGA.

### Claim 18 (depends on 11)

The apparatus of claim 11, wherein the apparatus further includes one of a hypervisor or operating system virtualization layer running on the processor, and the apparatus is further configured to provide at least one of capabilities and functions associated with the programmed FPGA to the hypervisor or OS virtualization layer.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the at least one of capabilities and functions associated with the programmed FPGA include one or more functions the FGPA is capable of performing that are provided to a hypervisor, wherein the apparatus is further configured to:
expose the one or more functions to at least one of a virtual machine hosted by the hypervisor or an operating system running on a virtual machine hosted by the processor; and
enable the operating system to access the FPGA to perform the one or more functions.

### Claim 20 (depends on 18)

The apparatus of claim 18, wherein the at least one of capabilities and functions associated with the programmed FPGA include one or more functions the FGPA is capable of performing that are provided to the OS virtualization layer, wherein the apparatus is further configured to:
expose the one or more functions to at least one of a container hosted by the OS virtualization layer and an application running in the container; and
enable the application to access the FPGA to perform the one or more functions.

### Claim 21

A non-transitory machine readable medium, having firmware instructions stored thereon, configured to be executed by a processor of a compute node having memory and a Field Programmable Gate Array (FPGA), the processor coupled to a management controller via a first link and to the FPGA via a second link, the compute node further having at least one of a fabric interface and a network interface, wherein the compute node is configured to be installed in a chassis, wherein when installed in the chassis said at least one of the fabric interface or network interface is coupled to a network or fabric, wherein the firmware instructions enable, upon execution, the compute node to:
one of receive or retrieve a pointer to an FPGA bitstream file from the management controller via the first link, the pointer to the FPGA bitstream file identifying a location at which the FGPA bitstream file is stored that is accessible via one of a fabric coupled to the fabric interface or a network coupled to the network interface, FPGA bitstream file including content comprising an FPGA bitstream,
retrieve the FPGA bitstream file from the location identified by the pointer, the FPGA bitstream file being retrieved by accessing one of the fabric or the network; and
stream the FPGA bitstream over the second link to the FPGA to program the FPGA.

### Claim 22 (depends on 21)

The non-transitory machine readable medium of claim 21, wherein the management controller is coupled to the processor via a first Peripheral Component Interconnect Express (PCIe) link, and the FPGA is coupled to the processor via a second PCIe link.

### Claim 23 (depends on 21)

The non-transitory machine readable medium of claim 21, wherein one of a hypervisor or operating system (OS) virtualization layer is running on the processor, wherein execution of the firmware instructions further enables the compute node to provide at least one of capabilities and functions associated with the programmed FPGA to the hypervisor or the OS virtualization layer.

### Claim 24 (depends on 23)

The non-transitory machine readable medium of claim 23, wherein the at least one of capabilities and functions associated with the programmed FPGA include one or more functions the FGPA is capable of performing that are provided to a hypervisor, wherein execution of the firmware instructions further enables the compute node to:
expose the one or more functions to at least one of a virtual machine hosted by the hypervisor or an operating system running on a virtual machine hosted by the processor; and
enable the operating system to access the FPGA to perform the one or more functions.

### Claim 25 (depends on 23)

The non-transitory machine readable medium of claim 23, wherein the at least one of capabilities and functions associated with the programmed FPGA include one or more functions the FGPA is capable of performing that are provided to the OS virtualization layer, wherein execution of the firmware instructions further enables the compute node to:
expose the one or more functions to at least one of a container hosted by the OS virtualization layer and an application running in the container; and
enable the application to access the FPGA to perform the one or more functions.