# US 2019/0173698 A1 · Direct current removal circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0173698 A1 - Document ID: US20190173698A1 - Status: Published application - Kind: A1 - Application number: 16/102,789 - Filed: 2018-08-14 - Published: 2019-06-06 - Earliest claimed: 2017-12-01 - Assignees: MStar Semiconductor, Inc. - Applicants: MStar Semiconductor, Inc. - Inventors: Teng-Han TSAI; Tai-Lai TUNG - Web page: https://patentgrep.com/patent/US20190173698A1 ## CPC - H04L 25/061: {providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of DC offset (removal of DC offset in coupling arrangements H04L25/029, H04L25/0296)} - H03D 3/008: {Compensating DC offsets} - H04B 1/0475: {with means for limiting noise, interference or distortion (H04B1/0483 takes precedence)} - H04B 1/12: Neutralising, balancing, or compensation arrangements - H04B 1/525: with means for reducing leakage of transmitter signal into the receiver - H04L 25/06: DC level restoring means; Bias distortion correction {; Decision circuits providing symbol by symbol detection} - H03D 2200/009: Reduction of local oscillator or RF leakage - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H03D: DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER (masers, lasers H01S; circuits capable of acting both as modulator and demodulator H03C; details applicable to both modulators and frequency-changers H03C; demodulating pulses H03K9/00; transforming types of pulse modulation H03K11/00; coding, decoding or code conversion, in general H03M; repeater stations H04B7/14; demodulators adapted for AC systems of digital information transmission H04L27/00; synchronous demodulators adapted for colour television H04N9/66) - H04B: TRANSMISSION ## Abstract A direct current (DC) removal circuit is coupled to a radio-frequency (RF) module, which includes a local oscillator. The DC removal circuit includes: a waveform generator, generating a digital waveform signal having an average value that is smaller than a resolution of a converter coupled to the RF module; a digital adder, coupled to the waveform generator, adding the digital waveform signal to a digital DC value to generate an addition result; and a digital subtractor, subtracting the addition result from a digital signal to generate a subtraction result, so as to compensate leakage caused by the local oscillator. ## Claims ### Claim 1 A direct current (DC) removal circuit, coupled to a radio-frequency (RF) module, the RF module comprising a local oscillator, the DC removal circuit for compensating leakage caused by the local oscillator, the DC removal circuit comprising: a waveform generator, generating a digital waveform signal having an average value, which is smaller than a resolution of a converter coupled to the RF module; a digital adder, coupled to the waveform generator, adding the digital waveform signal to a digital DC value to generate an addition result; and a digital subtractor, subtracting the addition result from a digital signal to generate a subtraction result so as to compensate the leakage caused by the local oscillator. ### Claim 2 (depends on 1) The DC removal circuit according to claim 1, provided at a transmitting end; wherein, the digital subtractor outputs the subtraction result to the converter, the converter converts the subtraction result to an analog signal, and the RF module generates a transmission signal according to the analog signal. ### Claim 3 (depends on 1) The DC removal circuit according to claim 1, provided at a receiving end; wherein, the RF module generates a reception signal, the converter converts the reception signal to the digital signal, and the DC removal circuit outputs the subtraction result. ### Claim 4 (depends on 1) The DC removal circuit according to claim 1, wherein the digital waveform signal is a periodical pulse sequence signal, there are N pulse widths and k positive pulses in one period of the digital waveform signal, and the waveform generator generates the digital waveform signal according to the number N of the pulse widths and the number k of positive pulses. ### Claim 5 (depends on 4) The DC removal circuit according to claim 4, wherein an amplitude of each positive pulse is associated with the resolution of the converter. ### Claim 6 (depends on 4) The DC removal circuit according to claim 4, wherein the waveform generator generates the digital waveform signal according to the number N of pulse widths and the number k of positive pulses by performing steps of: generating a counter signal; when a value of the counter signal is 0 or is greater than or equal to (N/k), the waveform generator outputting a positive pulse; and when the value of the counter signal is smaller than (N/k), the waveform generator outputting 0. ### Claim 7 (depends on 6) The DC removal circuit according to claim 6, wherein the waveform generator generates the counter signal by performing steps of: setting a value of a register to 0, adding the value of the register by 1 after each clock cycle, and storing the result in the register; when the value stored in the register is greater than or equal to (N/k), subtracting (N/k−1) from the value of the register, and storing the result in the register; and outputting the value of the register as the counter signal. ### Claim 8 (depends on 4) The DC removal circuit according to claim 4, wherein the waveform generator comprises: a counter signal generator, generating a clock signal, the counter signal generator setting a value of the register to 0, adding the value of the register by 1 after each clock cycle, and storing the result in the register; when the value of the register is greater than or equal to 1, the counter signal generator subtracting (N/k−1) from the value of the register, storing the result in the register, and outputting the value of the register as the counter signal; and an output unit, receiving the counter signal; wherein, when the value of the counter signal is 0 or is greater than or equal to (N/k), the waveform generator outputs a positive pulse; when the value of the counter signal is smaller than (N/k), the waveform generator outputs 0.