# US 2019/0173697 A1 · Methods and circuits for asymmetric distribution of channel equalization between devices

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- Number: US 2019/0173697 A1
- Document ID: US20190173697A1
- Status: Published application
- Kind: A1
- Application number: 16/182,724
- Filed: 2018-11-07
- Published: 2019-06-06
- Earliest claimed: 2006-12-05
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Jared L. Zerbe; Fariborz Assaderaghi; Brian S. Leibowitz; Hae-Chang Lee; Jihong Ren; Qi Lin
- Web page: https://patentgrep.com/patent/US20190173697A1

## CPC

- H04L 25/03343: {Arrangements at the transmitter end}
- H01J 37/00: Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof (H01J33/00, H01J40/00, H01J41/00, H01J47/00, H01J49/00 take precedence)
- H04L 25/03057: {with a recursive structure (H04L25/03031 takes precedence)}
- H04L 25/0307: {using blind adaptation}
- H04L 25/03885: {adaptive}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10P 50/283: {by chemical means}
- H10P 50/73: {using masks for insulating materials}
- H10P 72/0421: {for drying etching}
- H10P 72/722: {Details of electrostatic chucks}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H04L 2025/03356: {Baseband transmission}
- H04L 2025/03433: {characterised by equaliser structure}
- H04L 2025/03617: {Time recursive algorithms (H04L2025/03643 takes precedence)}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

## Claims

### Claim 1

(canceled)

### Claim 2

An integrated circuit comprising:
a transmit equalizer having a transmit-equalizer control port, the transmit equalizer to equalize a first signal resulting in a first equalized signal, using a first range of coefficients, applied to the transmit-equalizer control port;
a receive port to receive a corrupted second signal that includes inter-symbol interference;
a signal monitor to provide a measure of the inter-symbol interference of the second signal; and
equalization control circuitry coupled between the signal monitor and the transmit-equalizer control port.

### Claim 3 (depends on 2)

The integrated circuit of claim 2, further comprising a receive equalizer having a receive-equalizer control port, the receive equalizer to equalize the inter-symbol interference of the second signal.

### Claim 4 (depends on 3)

The integrated circuit of claim 3, wherein the equalization control circuitry is coupled to the receive-equalizer control port.

### Claim 5 (depends on 3)

The integrated circuit of claim 3, wherein the signal monitor is coupled to the receive port via the receive equalizer.

### Claim 6 (depends on 2)

The integrated circuit of claim 2, wherein the transmit equalizer includes a pre-cursor filter tap, and wherein the equalization control circuitry controls the pre-cursor filter tap based upon the measure of inter-symbol interference of the second signal.

### Claim 7

A method of transmitting a first signal from an integrated circuit, the method comprising:
receiving a corrupted second signal at a receiver pad of the integrated circuit;
measuring corruption of the second signal, the corruption including inter-symbol interference;
deriving a transmit coefficient from the measured corruption; and
adjusting the first signal using the transmit coefficient.

### Claim 8 (depends on 7)

The method of claim 7, further comprising deriving a receive coefficient from the measured corruption.

### Claim 9 (depends on 8)

The method of claim 8, further comprising calculating the transmit coefficient from the receive coefficient.

### Claim 10 (depends on 7)

The method of claim 7, further comprising measuring an amplitude of the corrupted second signal, wherein the deriving of the transmit coefficient is based at least in part on the amplitude.

### Claim 11 (depends on 7)

The method of claim 7, wherein first signal and the corrupted second signal are conveyed over a bidirectional channel.

### Claim 12 (depends on 7)

The method of claim 7, further comprising periodically updating the transmit coefficient.

### Claim 13 (depends on 7)

The method of claim 7, wherein the integrated circuit is a first integrated circuit and the second signal is received from a second integrated circuit, the method further comprising:
receiving a corrupted third signal at a receiver pad of the first integrated circuit from a third integrated circuit;
measuring second corruption of the third signal, the second corruption including second inter-symbol interference; and
deriving a second transmit coefficient from the measured second corruption; and
transmitting to the third integrated circuit using the second transmit coefficient.

### Claim 14

An integrated circuit comprising:
a transmitter having a transmit coefficient port, for receiving a transmit coefficient, and an output port for transmitting a first signal over a communication lane;
a receiver for receiving a corrupted second signal over the communication lane; and
means for deriving the transmit coefficient from the corrupted second signal.

### Claim 15 (depends on 14)

The integrated circuit of claim 14, wherein the corrupted second signal includes inter-symbol interference, and wherein the receiver further comprises a receive equalizer, the integrated circuit further comprising means for adjusting the receive equalizer responsive to the inter- symbol interference.

### Claim 16

A computer-readable medium having stored thereon non-transitory representation of a receiver, the representation comprising:
first data representing a transmit equalizer having a transmit-equalizer control port, the transmit equalizer to equalize a first signal resulting in a first equalized signal, using a first range of coefficients, applied to the transmit-equalizer control port;
second data representing a receive port to receive a corrupted second signal that includes inter-symbol interference;
third data representing a signal monitor to provide a measure of the inter-symbol interference of the second signal; and
fourth data representing equalization control circuitry coupled between the signal monitor and the transmit-equalizer control port.

### Claim 17 (depends on 16)

The computer-readable medium of claim 16, the representation further comprising fifth data representing a receive equalizer having a receive-equalizer control port, the receive equalizer to equalize the inter-symbol interference of the second signal.

### Claim 18 (depends on 17)

The computer-readable medium of claim 17, wherein the equalization control circuitry is represented as coupled to the receive-equalizer control port.

### Claim 19 (depends on 17)

The computer-readable medium of claim 17, wherein the signal monitor is represented as coupled to the receive port via the receive equalizer.

### Claim 20 (depends on 16)

The computer-readable medium of claim 16, wherein the first data represents the transmit equalizer as including a pre-cursor filter tap, and wherein the equalization control circuitry is represented as controlling the pre-cursor filter tap based upon the measure of inter-symbol interference of the second signal.