# US 2019/0173664 A1 · Signal detection techniques using clock data recovery

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- Number: US 2019/0173664 A1
- Document ID: US20190173664A1
- Status: Published application
- Kind: A1
- Application number: 16/036,227
- Filed: 2018-07-16
- Published: 2019-06-06
- Earliest claimed: 2016-12-28
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: AMIR LAUFER; ITAMAR LEVIN; KEVAN A. LILLIE
- Web page: https://patentgrep.com/patent/US20190173664A1

## CPC

- H04L 7/048: {using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal}
- H03L 7/0807: {concerning mainly a recovery circuit for the reference signal}
- H03L 7/091: the phase or frequency detector using a sampling device (H03L7/087 takes precedence)
- H04L 7/0079: {Receiver details}
- H04L 7/0083: {taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks}
- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

Techniques and apparatus for detection of a signal at an I/O interface module are described. In one embodiment, for example, an apparatus to provide signal detection may include at least one receiver, at least one memory, and logic for a signal detection module, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one receiver, the logic to access a plurality of pulse signals of a clock and data recovery (CDR) circuit, analyze at least one pulse characteristic of the plurality of pulse signals, and generate a signal determination to indicate a signal at the at least one receiver based on the at least one pulse characteristic. Other embodiments are described and claimed.

## Claims

### Claim 1

An apparatus to provide signal detection, the apparatus comprising:
at least one receiver;
at least one memory; and
logic for a signal detection module, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one receiver, the logic to:
access a plurality of pulse signals of a clock and data recovery (CDR) circuit,
analyze at least one pulse characteristic of the plurality of pulse signals, and
generate a signal determination to indicate a signal at the at least one receiver based on the at least one pulse characteristic.

### Claim 2 (depends on 1)

The apparatus of claim 1, the plurality of pulse signals generated by a phase detector of the CDR circuit.

### Claim 3 (depends on 1)

The apparatus of claim 1, the plurality of pulse signals comprising phase error signals generated by a phase detector of the CDR circuit.

### Claim 4 (depends on 1)

The apparatus of claim 1, the at least one pulse characteristic comprising a pulse count.

### Claim 5 (depends on 1)

The apparatus of claim 1, the at least one pulse characteristic comprising a pulse count,
the logic to generate an unable to track determination responsive to the pulse count being outside of a pulse count threshold.

### Claim 6 (depends on 1)

The apparatus of claim 1, the at least one pulse characteristic comprising a pulse directionality.

### Claim 7 (depends on 1)

The apparatus of claim 1, the at least one pulse characteristic comprising a pulse directionality,
the logic to generate an unable to center determination responsive to the pulse directionality being outside of a directionality threshold.

### Claim 8 (depends on 1)

The apparatus of claim 1, the logic to generate an invalid signal determination responsive to determining that a gain of a variable gain amplifier of the CDR is greater than a maximum gain threshold.

### Claim 9 (depends on 1)

The apparatus of claim 1, the logic to generate an invalid signal determination responsive to expiry of a signal detect timer.

### Claim 10 (depends on 1)

The apparatus of claim 1, the logic to provide the signal determination to at least one signal function.

### Claim 11

A method to provide signal detection, the method comprising:
accessing a plurality of pulse signals of a clock and data recovery (CDR) circuit;
analyzing at least one pulse characteristic of the plurality of pulse signals for; and
generating a signal determination to indicate a signal at a receiver communicatively coupled to the CDR, the signal determination based on the at least one pulse characteristic.

### Claim 12 (depends on 11)

The method of claim 11, the plurality of pulse signals generated by a phase detector of the CDR circuit.

### Claim 13 (depends on 11)

The method of claim 11, the plurality of pulse signals comprising phase error signals generated by a phase detector of the CDR circuit.

### Claim 14 (depends on 11)

The method of claim 11, the at least one pulse characteristic comprising a pulse count.

### Claim 15 (depends on 11)

The method of claim 11, comprising generating an unable to track determination responsive to a pulse count being outside of a pulse count threshold.

### Claim 16 (depends on 11)

The method of claim 11, the at least one pulse characteristic comprising a pulse directionality.

### Claim 17 (depends on 11)

The method of claim 11, comprising generating an unable to center determination responsive to a pulse directionality being outside of a directionality threshold.

### Claim 18 (depends on 11)

The method of claim 11, comprising generating an invalid signal determination responsive to determining that a gain of a variable gain amplifier of the CDR is greater than a maximum gain threshold.

### Claim 19 (depends on 11)

The method of claim 11, comprising generating an invalid signal determination responsive to expiry of a signal detect timer.

### Claim 20 (depends on 11)

The method of claim 11, comprising providing the signal determination to at least one signal function.

### Claim 21

A computer-readable storage medium that stores instructions for execution by processing circuitry of a computing device for signal detection, the instructions to cause the computing device to:
access a plurality of pulse signals of a clock and data recovery (CDR) circuit,
analyze at least one pulse characteristic of the plurality of pulse signals, and
generating a signal determination to indicate a signal at a receiver communicatively coupled to the CDR, the signal determination based on the at least one pulse characteristic.

### Claim 22 (depends on 21)

The computer-readable storage medium of claim 21, the plurality of pulse signals comprising phase error signals generated by a phase detector of the CDR circuit.

### Claim 23 (depends on 21)

The computer-readable storage medium of claim 21, the at least one pulse characteristic comprising a pulse count.

### Claim 24 (depends on 21)

The computer-readable storage medium of claim 21, the at least one pulse characteristic comprising a pulse directionality.

### Claim 25 (depends on 21)

The computer-readable storage medium of claim 21, the instructions to cause the computing device to provide the signal determination to at least one signal function.