# US 2019/0173660 A1 · Data communication system, data communication apparatus, and sensor apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0173660 A1 - Document ID: US20190173660A1 - Status: Published application - Kind: A1 - Application number: 16/266,840 - Filed: 2019-02-04 - Published: 2019-06-06 - Earliest claimed: 2015-06-15 - Assignees: Fuji Electric Co., Ltd. - Applicants: Fuji Electric Co., Ltd. - Inventors: Masashi AKAHANE - Web page: https://patentgrep.com/patent/US20190173660A1 ## CPC - H04L 7/0008: {Synchronisation information channels, e.g. clock distribution lines} - G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom - G06F 1/10: Distribution of clock signals {, e.g. skew} - G06F 13/40: Bus structure {(for computer networks G06F15/163; for optical bus networks H04B10/25)} - H03K 17/567: Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT - H04B 3/02: Details - H04L 25/49: using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels {; Baseband coding techniques specific to data transmission systems (spectral shaping H04L25/03828)} - H04Q 9/00: Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom - H04Q 2209/30: using a wired architecture - H04Q 2209/70: Arrangements in the main station, i.e. central controller - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H04B: TRANSMISSION - H04Q: SELECTING (switches, relays, selectors H01H; wireless communication networks H04W) ## Abstract A system is connected to a single-wire communication line to perform bidirectional communication between a master side and a slave side, and an input clock-side transistor connected between a GND level and the communication line performs switching according to an input clock. A first transistor is connected between a first potential and the communication line, a second transistor has one end connected to a second potential, and a master-side resistor is connected between the other end of the second transistor and the other end of a third transistor. A fourth transistor is connected between the communication line and a third potential equal to or higher than the first potential, and a slave-side resistor is connected between the communication line and the GND level. ## Claims ### Claim 1 A data communication system comprising: a master-side data communication apparatus configured to perform bidirectional communication with a slave side via a single-wire communication line; and a slave-side data communication apparatus configured to perform bidirectional communication with the master-side data communication apparatus via the single-wire communication line, wherein the master-side data communication apparatus includes: an input clock-side transistor connected between a reference potential and the single-wire communication line, and configured to perform switching according to an input clock; a first transistor connected between a first potential and the single-wire communication line; a second transistor having one end connected to a second potential lower than the first potential; a third transistor having one end connected to the second potential; a master-side resistor connected between another end of the second transistor and another end of the third transistor; and a master-side data reproduction circuit configured to reproduce data transmitted from the slave-side data communication apparatus via the single-wire communication line, wherein the slave-side data communication apparatus includes: a fourth transistor connected between the single-wire communication line and a third potential equal to or higher than the first potential; a clock reproduction circuit configured to reproduce a clock transmitted from the master-side data communication apparatus via the single-wire communication line; and a slave-side data reproduction circuit configured to reproduce data transmitted from the master-side data communication apparatus via the single-wire communication line. ### Claim 2 (depends on 1) The data communication system according to claim 1, wherein the input clock-side transistor turns on when the input clock is at a low potential level, to set a potential on the single-wire communication line to the reference potential, the first transistor, at a time of transmission of master-side data from a master side to the slave side, when the master-side data, a master-side enable signal, and the input clock are set to a high potential level, is turned on by a first condition signal to set a potential on the single-wire communication line to the first potential, the second transistor, at a time of writing the master-side data transmitted from the master side to the slave side, when the master-side data is set to the low potential level and the master-side enable signal and the input clock are set to the high potential level, is turned on by a second condition signal to set the potential on the single-wire communication line to the second potential, the third transistor, at a time of reading the data transmitted from the slave-side data communication apparatus by the master side, when the master-side enable signal is set to the low potential level, is turned on by a third condition signal to set the single-wire communication line to a pull-up state with the second potential via the master-side resistor, and the fourth transistor, at the time of reading the data transmitted from the slave-side data communication apparatus by the master side, when the transmitted data, a slave-side enable signal, and the clock reproduced by the clock reproduction circuit are set to the high potential level, is turned on by a fourth condition signal to set the potential on the single-wire communication line to the third potential. ### Claim 3 (depends on 1) The data communication system according to claim 1, wherein the master-side data reproduction circuit includes a first comparator, one input end of the first comparator is connected to the single-wire communication line, and an intermediate potential between the first potential and the second potential is input to another input end of the first comparator, and the slave-side data reproduction circuit includes a second comparator, and one input end of the second comparator is connected to the single-wire communication line, and an intermediate potential between the third potential and the second potential is input to another input end of the second comparator. ### Claim 4 (depends on 1) The data communication system according to claim 1, wherein the fourth transistor, when an abnormality occurs in the slave-side data communication apparatus, autonomously turns on to set a potential on the single-wire communication line to the third potential, and notifies the master-side data communication apparatus of the abnormality. ### Claim 5 (depends on 1) The data communication system according to claim 1, wherein the slave-side data communication apparatus transmits a high potential level to the master-side data communication apparatus when operating with a normal power supply, and outputs a GND level when not operating with the normal power supply, and the master-side data communication apparatus recognizes a power supply state of the slave-side data communication apparatus by determining whether or not the slave-side data communication apparatus is able to transmit the high potential level. ### Claim 6 A data communication apparatus that performs bidirectional communication with a slave side via a single-wire communication line, comprising: an input clock-side transistor connected between a reference potential and the single-wire communication line, and configured to perform switching according to an input clock; a first transistor connected between a first potential and the single-wire communication line; a second transistor having one end connected to a second potential lower than the first potential; a third transistor having one end connected to the second potential; a master-side resistor connected between another end of the second transistor and another end of the third transistor; and a master-side data reproduction circuit configured to reproduce data transmitted from the slave side via the single-wire communication line. ### Claim 7 A data communication apparatus that performs bidirectional communication with a master side via a single-wire communication line, comprising: a transistor connected between the single-wire communication line and a slave-side potential equal to or higher than a master-side potential supplied to the master side; a clock reproduction circuit configured to reproduce a clock transmitted from the master side via the single-wire communication line; and a slave-side data reproduction circuit configured to reproduce data transmitted from the master side via the single-wire communication line, wherein the transistor is configured to be turned on or off by a signal that is a result of a logical operation on the reproduced clock, an enable signal of the data communication apparatus, and a data signal transmitted by the data communication apparatus to the master side, such that when an abnormality occurs in the data communication apparatus, the transistor autonomously turns on to set a potential on the single-wire communication line to a high potential level, and notifies the master-side of the abnormality. ### Claim 8 A sensor apparatus that performs bidirectional communication with a master side via a single-wire communication line and detects a physical quantity, comprising: an interface circuit including a transistor connected between the single-wire communication line and a slave-side potential equal to or higher than a master-side potential supplied to the master side, a clock reproduction circuit configured to reproduce a clock transmitted from the master side via the single-wire communication line, and a slave-side data reproduction circuit configured to reproduce data transmitted from the master side via the single-wire communication line, and configured to communicate with the master side via the single-wire communication line; a sensor element configured to generate an electrical signal according to the detected physical quantity; an amplification circuit configured to amplify the electrical signal; an auxiliary memory configured to temporarily store input trimming data; a main memory configured to store, by an electric write operation, the input trimming data stored in the auxiliary memory; an adjustment circuit configured to adjust output characteristics of the sensor element on the basis of the input trimming data stored in the auxiliary memory, or the input trimming data stored in the main memory; and a control circuit configured to determine a control mode of the main memory, and the sensor apparatus having, as apparatus terminals: a single output terminal for outputting the electrical signal amplified by the amplification circuit to an outside; a single input/output interface terminal connected to the single-wire communication line for receiving trimming clocks in order to determine the input trimming data to be written to the main memory, and also inputting and outputting data; and a plurality of voltage application terminals for applying a voltage when writing data to the main memory. ### Claim 9 A data communication apparatus that performs bidirectional communication with a master side via a single-wire communication line, comprising: a transistor connected between the single-wire communication line and a slave-side potential equal to or higher than a master-side potential supplied to the master side; a clock reproduction circuit configured to reproduce a clock transmitted from the master side via the single-wire communication line; and a slave-side data reproduction circuit configured to reproduce data transmitted from the master side via the single-wire communication line, wherein the transistor is configured to be turned on or off by a signal that is a result of a logical operation on the reproduced clock, an enable signal of the data communication apparatus, and a data signal transmitted by the data communication apparatus to the master side, such that the data communication apparatus transmits a high potential level to the master side when operating with a normal power supply, and outputs a GND level when not operating with the normal power supply, and the master side recognizes a power supply state of the data communication apparatus by determining whether or not the data communication apparatus is able to transmit the high potential level. ### Claim 10 (depends on 9) The data communication apparatus of claim 9, wherein the logical operation is NAND.