# US 2019/0173519 A1 · Systems and methods for ultra wideband impulse radio receivers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0173519 A1 - Document ID: US20190173519A1 - Status: Published application - Kind: A1 - Application number: 16/260,334 - Filed: 2019-01-29 - Published: 2019-06-06 - Earliest claimed: 2015-06-01 - Assignees: Transfert Plus, Societe en Commandite - Applicants: Transfert Plus Societe En Commandite - Inventors: FREDERIC NABKI; DOMINIC DESLANDES; MOHAMMAD TAHERZADEH-SANI; MICHIEL SOER - Web page: https://patentgrep.com/patent/US20190173519A1 ## CPC - H04B 1/717: Pulse-related aspects - H04B 1/1615: {Switching on; Switching off, e.g. remotely (battery saving circuits associated with selective call operation H04W52/00; details of power consumption reduction in a PLL, H03L7/0802, H03L7/14, H03L2207/08, H03L2207/18; muting amplifiers by gain control see H03G3/34)} - H04B 1/385: {Transceivers carried on the body, e.g. in helmets} - H04B 1/7163: using impulse radio - H04B 1/7183: Synchronisation - H04L 1/0057: {Block codes (H04L1/0061, H04L1/0064 take precedence)} - H04L 5/0044: {Allocation of payload; Allocation of data channels, e.g. PDSCH or PUSCH} - H04L 7/00: Arrangements for synchronising receiver with transmitter {(synchronisation of generators of electric oscillations or pulses H03L7/00)} - H04L 7/0091: {Transmitter details} - H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop - H04L 25/00: Baseband systems - H04L 25/03834: {using pulse shaping} - H04L 25/4902: {Pulse width modulation; Pulse position modulation} - H04L 27/22: Demodulator circuits; Receiver circuits - H04L 27/2647: {Arrangements specific to the receiver only (equalisation H04L27/01)} - Y02D 30/70: in wireless communication networks - H04B: TRANSMISSION - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Ultra-Wideband (UWB) technology exploits modulated coded impulses over a wide frequency spectrum with very low power over a short distance for digital data transmission. Today's leading edge modulated sinusoidal wave wireless communication standards and systems achieve power efficiencies of 50 nJ/bit employing narrowband signaling schemes and traditional RF transceiver architectures. However, such designs severely limit the achievable energy efficiency, especially at lower data rates such as below 1 Mbps. Further, it is important that peak power consumption is supportable by common battery or energy harvesting technologies and long term power consumption neither leads to limited battery lifetimes or an inability for alternate energy sources to sustain them. Accordingly, it would be beneficial for next generation applications to exploit inventive transceiver structures and communication schemes in order to achieve the sub nJ per bit energy efficiencies required by next generation applications. ## Claims ### Claim 1 A receiver comprising: a receiver circuit coupled to the antenna for processing received ultra-wideband wireless signals and generating an output electrical signal in dependence upon the received ultra-wideband wireless signals; wherein the received ultra-wideband wireless signals are coupled from an antenna. ### Claim 2 (depends on 1) The receiver according to claim 1, wherein the receiver circuit comprises: a front end amplification circuit; a first squaring mixer for converting the ultra-wideband wireless signals to intermediate frequency signals; a variable gain amplifier for amplifying the intermediate frequency signals; a second squaring mixer for converting the amplified intermediate frequency signals to baseband frequency signals; and a digital processor for generating digital signals from the baseband frequency signals. ### Claim 3 (depends on 1) The receiver according to claim 1, wherein the receiver circuit comprises a receiver chain utilizing an instantaneous bandwidth of a first predetermined bandwidth of each individual pulse within a plurality of pulses within the received ultra-wideband wireless signals; a total bandwidth of the plurality of pulses within the received ultra-wideband wireless signals covers a second predetermined bandwidth; the plurality of pulses comprises one or more bits of a data signal encoded within the received ultra-wideband wireless signals; and each bit of the data signal is encoded as a pulse bundle comprising multiple pulses where each pulse is characterised by real-time configurable parameters of at least one of phase, frequency, amplitude and bandwidth. ### Claim 4 (depends on 3) The receiver according to claim 3, wherein the multiple pulses for a first bit of the data signal have a first spectral shape; and the multiple pulses for a second bit of the data signal have a second spectral shape. ### Claim 5 (depends on 3) The receiver according to claim 3, wherein each pulse within the plurality of pulses processed by the receiver chain have either a first phase or a second phase where the sequence of phases for the plurality of pulses being pseudo-random; and the width of each pulse within the plurality of pulses is randomly dithered. ### Claim 6 (depends on 1) The receiver according to claim 1, wherein the receiver circuit comprises: a first squaring mixer for converting the ultra-wideband wireless signals to intermediate frequency signals; and a second squaring mixer for converting the amplified intermediate frequency signals to baseband frequency signals. ### Claim 7 (depends on 6) The receiver according to claim 6, wherein each of the first squaring mixer and second squaring mixer receives a pair of differential signals; a first differential signal of the pair of differential signals is coupled to a gate of a first transistor and a first transistor within each of a first cross-coupled transistor pair and a second cross-coupled transistor; a second differential signal of the pair of differential signals is coupled to a gate of a second transistor and a second transistor within each of the first cross-coupled transistor pair and the second cross-coupled transistor; the sources of the first cross-coupled transistor pair are connected and coupled to the drain of the first transistor; the sources of the second cross-coupled transistor pair are connected and coupled to the drain of the second transistor. ### Claim 8 (depends on 6) The receiver according to claim 6, wherein the second squaring mixer allows the entire down converted pulse energy of each pulse of a plurality of pulses within the received ultra-wideband wireless signals to be coupled to an energy detector. ### Claim 9 (depends on 6) The receiver according to claim 6, further comprising a high pass filter coupled to an output of the first squaring mixer; an input of an AC-coupled variable gain amplifier coupled to an output of the high pass filter; and an input of the second squaring mixer is coupled to an output of the AC-coupled variable gain amplifier. ### Claim 10 (depends on 1) The receiver according to claim 1, wherein the receiver circuit comprises: a first portion for processing the received ultra-wideband wireless signals to generate converted received signals; and a second portion for processing the converted received signals to a plurality of digital signals; wherein the second portion of the receiver circuit comprises a clock generator for generating a plurality of clock signals and a decision circuit generating the plurality of digital signals in dependence upon the converted received signals and the plurality of clock signals; and the plurality of clock signals are at a frequency determined in dependence upon a symbol rate for bits of data encoded within the ultra-wideband received wireless signals. ### Claim 11 (depends on 10) The receiver according to claim 10, wherein the clock generator comprises: a low frequency oscillator generating a sinusoidal oscillator signal at a first predetermined frequency; a converter circuit for converting the sinusoidal oscillator signal at the first predetermined frequency to a square wave clock at the first predetermined frequency; and a phase locked loop for generating an output clock signal at a second predetermined frequency. ### Claim 12 (depends on 10) The receiver according to claim 10, wherein the phase locked loop comprises a voltage controlled oscillator (VCO), a divider circuit, a phase detector, and a charge pump; wherein an output of the VCO comprises a clock signal at a third predetermined frequency and is coupled to an output of the clock generate and to an input of the divider circuit; an output of the divider circuit comprising the clock signal divided in frequency by the divider circuit is coupled to a first input port of the phase detector; the output clock signal at the second predetermined frequency is coupled to a second input port of the phase detector; an output of the phase detector comprising pulses generated in dependence upon whether the divided clock is coupled to the charge pump; the charge pump filters the pulses to generate a control signal for the VCO. ### Claim 13 (depends on 10) The receiver according to claim 10, wherein the decision circuit comprises: a first circuit comprising a first integration circuit for receiving the baseband frequency signals and a first analog-to-digital converter (ADC) circuit coupled to the output of the first integration circuit; a second circuit comprising a second integration circuit for receiving the baseband frequency signals and a second ADC circuit coupled to the output of the second integration circuit; ### Claim 14 (depends on 13) The receiver according to claim 13, wherein the first integration circuit receives a first clock signal of the plurality of clock signals; the second integration circuit receives a second clock signal of the plurality of clock signals; the first ADC circuit receives a third clock signal of the plurality of clock signals; the second ADC circuit receives a fourth clock signal of the plurality of clock signals; the first integration circuit integrates over a first half of a symbol period for the bits of data encoded within the ultra-wideband received wireless signals; the second integration circuit integrates over a second half of the symbol period for the bits of data encoded within the ultra-wideband received wireless signals; the first ADC circuit and second output ADC circuit are offset by a quarter of the symbol period; and the decision circuit generates digitized outputs for four overlapping integration windows within the symbol period. ### Claim 15 (depends on 1) The receiver according to claim 1, wherein the receiver is synchronised with a transmitter generating the ultra-wideband wireless signals independent of distributed timing information from the transmitter. ### Claim 16 (depends on 1) The receiver according to claim 1, wherein the receiver is synchronised with a transmitter generating the ultra-wideband wireless signals independent of distributed timing information from the transmitter; and the receiver synchronization employs an algorithm for synchronization with low latency and supporting aggressive power cycling of the receiver. ### Claim 17 (depends on 1) The receiver according to claim 1, wherein the ultra-wideband received wireless signals received from a wireless transmitter comprise a synchronization frame block; the receiver circuit generates a plurality of digitized outputs; each digitized output of the plurality of digitized outputs associated with an integration window of a plurality of overlapping integration windows; and the receiver circuit synchronizes a clock forming part of the receiver circuit to the wireless transmitter by determining the integration window of the plurality of overlapping integration windows with maximum energy. ### Claim 18 (depends on 17) The receiver according to claim 17, wherein synchronization of the clock within the receiver circuit to the wireless transmitter is achieved within one synchronization symbol within the synchronization frame block. ### Claim 19 (depends on 18) The receiver according to claim 18, wherein additional synchronization symbol within the synchronization frame block subsequent to the synchronization symbol within the synchronization frame block providing clock synchronization are employed within a variable gain loop within the receiver circuit to track changes in the channel of a wireless link formed between the wireless transmitter and the receiver. ### Claim 20 (depends on 17) The receiver according to claim 17, wherein the receiver circuit supports both demodulation of Pulse Position Modulation (PPM) and demodulation of On-Off Shift Keying Modulation (OOK) without reconfiguration; PPM demodulation is performed by observing which integration window within the plurality of integration windows has the maximum energy; and OOK demodulation is performed by observing the energy within a fixed integration window of the plurality of overlapping integration windows.