# US 2019/0173516 A1 · Clock and data recovery circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0173516 A1 - Document ID: US20190173516A1 - Status: Published application - Kind: A1 - Application number: 16/261,376 - Filed: 2019-01-29 - Published: 2019-06-06 - Earliest claimed: 2017-08-16 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Po-Hsiang LAN; Cheng-Hsiang Hsieh - Web page: https://patentgrep.com/patent/US20190173516A1 ## CPC - H04B 1/7085: using a code tracking loop, e.g. a delay-locked loop - H04L 7/0025: {interpolation of clock signal} - H03L 7/07: using several loops, e.g. for redundant clock signal generation - H03L 7/0807: {concerning mainly a recovery circuit for the reference signal} - H03L 7/0814: {the phase shifting device being digitally controlled} - H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) - H04L 7/0029: {interpolation of received data signal} - H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop - H04B 2201/7073: Direct sequence modulation synchronisation - H04B: TRANSMISSION - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle. ## Claims ### Claim 1 A circuit, comprising: a finite state machine (FSM) that comprises: a first accumulator configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle, a second accumulator coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle, and a third accumulator coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the first accumulator comprises: a first flip flop configured to store a first phase code at a previous FSM cycle; a first adder configured to add the first phase code at the previous FSM cycle and the input phase code at current FSM cycle to generate the first phase code at the current FSM cycle; and a first filter configured to modify the first phase code at the current FSM cycle to generate the first order phase code at the current FSM cycle. ### Claim 3 (depends on 2) The circuit of claim 2, wherein the second accumulator comprises: a second flip flop configured to store a second phase code at a previous FSM cycle; a second adder configured to add the second phase code at the previous FSM cycle, the first order phase code at the current FSM cycle, and the input phase code at the current FSM cycle to generate the second phase code at the current FSM cycle; and a second filter configured to modify the second phase code at the current FSM cycle to generate the second order phase code at the current FSM cycle. ### Claim 4 (depends on 3) The circuit of claim 3, wherein the third accumulator comprises: a third filter configured to modify the input phase code to generate a modified input phase code at the current FSM cycle; a third flip flop configured to store a third phase code at a previous FSM cycle; and a third adder configured to add the third phase code at the previous FSM cycle, the second order phase code at the current FSM cycle, and the modified input phase code at the current FSM cycle to generate the third order phase code at the current FSM cycle. ### Claim 5 (depends on 1) The circuit of claim 1, further comprising: a phase interpolator configured to rotate a phase of the clock signal to provide a rotated clock, wherein the phase is linearly correlated to the third order phase code. ### Claim 6 (depends on 1) The circuit of claim 1, further comprising: a divider configured to slow down an initial clock provided by the phase interpolator to generate the clock signal; and a deserializer configured to convert the data signal from a serial format into a parallel format and to generate the input phase code representing the phase timing difference between the data signal and the clock signal. ### Claim 7 (depends on 6) The circuit of claim 6, wherein: the divider is further configured to slow down the rotated clock provided by the phase interpolator to generate an updated clock signal; and the deserializer is further configured to convert an updated data signal from a serial format into a parallel format and to update the input phase code to represent a phase timing difference between the updated data signal and the updated clock signal. ### Claim 8 (depends on 6) The circuit of claim 6, wherein the FSM further comprises: a fourth flip flop configured to store the input phase code generated by the deserializer and to provide the stored input phase code to the first accumulator, the second accumulator, and the third accumulator at each FSM cycle. ### Claim 9 (depends on 1) The circuit of claim 1, wherein the FSM has a closed loop transfer function that cancels residual jitter of the circuit. ### Claim 10 (depends on 1) The circuit of claim 1, wherein the FSM has a phase margin higher than or equal to 60 degrees. ### Claim 11 A circuit, comprising: a finite state machine (FSM) that comprises: a first accumulator configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle, and a second accumulator coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle; and a phase interpolator configured to rotate a phase of the clock signal to provide a rotated clock based on the second order phase code. ### Claim 12 (depends on 11) The circuit of claim 11, wherein the first accumulator comprises: a first flip flop configured to store a first phase code at a previous FSM cycle; a first adder configured to add the first phase code at the previous FSM cycle and the input phase code at current FSM cycle to generate the first phase code at the current FSM cycle; and a first filter configured to modify the first phase code at the current FSM cycle to generate the first order phase code at the current FSM cycle. ### Claim 13 (depends on 12) The circuit of claim 12, wherein the second accumulator comprises: a second flip flop configured to store a second phase code at a previous FSM cycle; a second adder configured to add the second phase code at the previous FSM cycle, the first order phase code at the current FSM cycle, and the input phase code at the current FSM cycle to generate the second phase code at the current FSM cycle; and a second filter configured to modify the second phase code at the current FSM cycle to generate the second order phase code at the current FSM cycle. ### Claim 14 (depends on 1) The circuit of claim 1, further comprising: a divider configured to slow down an initial clock provided by the phase interpolator to generate the clock signal; and a deserializer configured to convert the data signal from a serial format into a parallel format and to generate the input phase code representing the phase timing difference between the data signal and the clock signal. ### Claim 15 (depends on 14) The circuit of claim 14, wherein: the divider is further configured to slow down the rotated clock provided by the phase interpolator to generate an updated clock signal; and the deserializer is further configured to convert an updated data signal from a serial format into a parallel format and to update the input phase code to represent a phase timing difference between the updated data signal and the updated clock signal. ### Claim 16 (depends on 1) The circuit of claim 1, wherein the FSM has at least one of: a closed loop transfer function that cancels residual jitter of the circuit; and a phase margin higher than or equal to 60 degrees. ### Claim 17 A method, comprising: generating an input phase code representing a phase timing difference between a data signal and a clock signal at each finite state machine (FSM) cycle; accumulating input phase codes for different FSM cycles to generate a first order phase code at each FSM cycle; accumulating the input phase codes and first order phase codes for different FSM cycles to generate a second order phase code at each FSM cycle; accumulating the input phase codes and second order phase codes for different FSM cycles to generate a third order phase code at each FSM cycle. ### Claim 18 (depends on 17) The method of claim 17, further comprising: slowing down an initial clock to generate the clock signal; and converting the data signal from a serial format into a parallel format. ### Claim 19 (depends on 17) The method of claim 17, further comprising: rotating a phase of the clock signal to provide a rotated clock, wherein the phase is linearly correlated to the third order phase code. ### Claim 20 (depends on 19) The method of claim 19, further comprising: slowing down the rotated clock to generate an updated clock signal; converting an updated data signal from a serial format into a parallel format; and updating the input phase code to represent a phase timing difference between the updated data signal and the updated clock signal.