# US 2019/0173484 A1 · Reference disturbance mitigation in successive approximation register analog to digital converter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0173484 A1 - Document ID: US20190173484A1 - Status: Published application - Kind: A1 - Application number: 16/174,118 - Filed: 2018-10-29 - Published: 2019-06-06 - Earliest claimed: 2016-12-23 - Assignees: Avnera Corporation - Applicants: Avnera Corporation - Inventors: Wai Lee; Jianping Wen; Garry N. Link - Web page: https://patentgrep.com/patent/US20190173484A1 ## CPC - H03M 1/462: {Details of the control circuitry, e.g. of the successive approximation register} - H03M 1/0678: {using additional components or elements, e.g. dummy components} - H03M 1/08: of noise {(H03M1/0617 takes precedence)} - H03M 1/0863: {of switching transients, e.g. glitches} - H03M 1/442: {using switched capacitors} - H03M 1/468: {in which the input S/H circuit is merged with the feedback DAC array} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract The disclosure includes a mechanism for mitigating charge related disturbances in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by providing a fine reference connection and a rough reference connection. A switch array is activated to couple a current bit capacitor of a capacitor array to the rough reference connection while a current bit corresponding to the current bit capacitor is determined by a comparator. The switch array is further activated to couple a previous bit capacitor of the capacitor array to the fine reference connection while the current bit capacitor is coupled to the rough reference connection. This separates charge flow on the rough reference connection from capacitors coupled to the fine reference connection. ## Claims ### Claim at position 1 1-20. (canceled) ### Claim 21 A successive approximation register analog to digital converter for use at an analog output, the successive approximation register analog to digital converter comprising: a comparator; a capacitor array coupled to an input of the comparator; and a switch array configured to be activated to couple a current bit capacitor of the capacitor array to a rough reference connection while a current bit corresponding to the current bit capacitor is determined by the comparator, and to couple a previous bit capacitor of the capacitor array to a fine reference connection while the current bit capacitor is coupled to the rough reference connection. ### Claim 22 (depends on 21) The successive approximation register of claim 21 wherein to couple a previous bit capacitor of the capacitor array to a fine reference connection includes to simultaneously couple a group of previous bit capacitors while the current bit capacitor is coupled to the rough reference connection. ### Claim 23 (depends on 22) The successive approximation register of claim 22 wherein the group of previous bit capacitors includes a most significant bit capacitor. ### Claim 24 (depends on 22) The successive approximation register of claim 22 wherein the group of previous bit capacitors includes a specified number of largest capacitors in the capacitor array. ### Claim 25 (depends on 21) The successive approximation register of claim 21 wherein activation of the switch array does not couple a least significant bit capacitor of the capacitor array to the fine reference. ### Claim 26 (depends on 21) The successive approximation register of claim 21 wherein activation of the switch array does not couple a number of smallest capacitors of the capacitor array to the fine reference. ### Claim 27 A semiconductor die assembly comprising: a comparator mounted on a semiconductor die; a capacitor array, the capacitor array mounted on the semiconductor die; a switch array mounted on the semiconductor die; and a successive approximation register sequencer configured to activate the switch array to couple a current bit capacitor of the capacitor array to a rough reference connection while a current bit corresponding to the current bit capacitor is determined by the comparator, and further configured to activate the switch array to couple a previous bit capacitor of the capacitor array to a fine reference connection while the current bit capacitor is coupled to the rough reference connection, the successive approximation register sequencer mounted on the semiconductor die. ### Claim 28 (depends on 27) The die assembly of claim 27 wherein coupling the previous bit capacitor to the fine reference connection includes coupling a group of previous bit capacitors while the current bit capacitor is coupled to the rough reference connection. ### Claim 29 (depends on 28) The die assembly of claim 28 wherein the group of previous bit capacitors includes a most significant bit capacitor. ### Claim 30 (depends on 28) The die assembly of claim 28 wherein the group of previous bit capacitors includes a specified number of largest capacitors in the capacitor array. ### Claim 31 (depends on 27) The die assembly of claim 27 wherein the successive approximation register sequencer is further configured to activate the switch array such that the switch array does not couple a least significant bit capacitor to the fine reference. ### Claim 32 (depends on 27) The die assembly of claim 27 wherein the successive approximation register sequencer is further configured to activate the switch array such that the switch array does not couple a specified number of smallest capacitors to the fine reference. ### Claim 33 (depends on 27) The die assembly of claim 27 wherein the fine reference connection includes a fine positive reference connection, a fine negative reference connection, or combinations thereof. ### Claim 34 (depends on 27) The die assembly of claim 27 wherein the rough reference connection includes a rough positive reference connection, a rough negative reference connection, or combinations thereof. ### Claim 35 An analog to digital converter circuit assembly comprising: a comparator; a capacitor array; a switch array configured to selectively couple the capacitor array to an analog signal input and to reference connections; and a successive approximation register sequencer configured to activate the switch array to couple a current bit capacitor of the capacitor array to a rough reference connection while a current bit corresponding to the current bit capacitor is determined by the comparator, and further configured to activate the switch array to couple a previous bit capacitor of the capacitor array to a fine reference connection while the current bit capacitor is coupled to the rough reference connection. ### Claim 36 (depends on 35) The circuit assembly of claim 35 wherein the successive approximation register sequencer is further configured to activate the switch array to couple a previous bit capacitor of the capacitor array to a fine reference connection and simultaneously coupling a group of previous bit capacitors while the current bit capacitor is coupled to the rough reference connection. ### Claim 37 (depends on 36) The circuit assembly of claim 36 wherein the group of previous bit capacitors includes a most significant bit capacitor. ### Claim 38 (depends on 36) The circuit assembly of claim 36 wherein the group of previous bit capacitors includes a specified number of largest capacitors in the capacitor array. ### Claim 39 (depends on 35) The circuit assembly of claim 35 wherein the successive approximation register sequencer is further configured to activate the switch array such that the switch array does not couple a least significant bit capacitor to the fine reference. ### Claim 40 (depends on 35) The circuit assembly of claim 35 wherein the successive approximation register sequencer is further configured to activate the switch array such that the switch array does not couple a specified number of smallest capacitors to the fine reference.