# US 2019/0173478 A1 · Method and apparatus to reduce effect of dielectric absorption in sar adc

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- Number: US 2019/0173478 A1
- Document ID: US20190173478A1
- Status: Published application
- Kind: A1
- Application number: 16/263,964
- Filed: 2019-01-31
- Published: 2019-06-06
- Earliest claimed: 2016-09-21
- Assignees: Analog Devices Global
- Applicants: Analog Devices Global
- Inventors: Sandeep Monangi; Mahesh Madhavan
- Web page: https://patentgrep.com/patent/US20190173478A1

## CPC

- H03M 1/0617: {characterised by the use of methods or means not specific to a particular type of detrimental influence}
- H03M 1/1042: {the look-up table containing corrected values for replacing the original digital values (H03M1/1052 takes precedence)}
- H03M 1/1245: {Details of sampling arrangements or methods}
- H03M 1/38: sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14)
- H03M 1/468: {in which the input S/H circuit is merged with the feedback DAC array}
- H03M 3/378: {Testing}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A successive approximation register analog to digital converter (SAR ADC) is provided in which impact of dielectric absorption is reduced with a correction circuit configured to adjust a present digital code value signal based at least in part upon a previous digital code value signal, an acquisition time and temperature.

## Claims

### Claim 1

A successive approximation analog to digital converter comprising:
a positive digital to analog converter (PDAC) and a negative digital to analog converter (NDAC) configured to provide respective test signals in response to each of multiple analog input signals; and
shuffle control switch circuitry configured to shuffle a first capacitor between a coupling of the first capacitor within the PDAC and a coupling of the first capacitor within the NDAC after each conversion by the PDAC and NDAC of a selected one of the analog input signals to the respective test signals.

### Claim 2 (depends on 1)

The converter of claim 1, wherein the converter includes a differential comparator, further including:
a control circuit coupled to receive comparison signals provided from the differential comparator and to provide control signals to cause the shuffle control switch circuitry to shuffle the first capacitor between each conversion by the PDAC and NDAC.

### Claim 3 (depends on 1)

The converter of claim 1, wherein the shuffle control switch circuitry is further configured to shuffle a second capacitor between a coupling of the second capacitor within the PDAC and a coupling of the second capacitor within the NDAC after each conversion by the PDAC and NDAC, wherein the shuffle control switch circuitry is configured to selectably shuffle the first capacitor and the second capacitor between the PDAC and the NDAC.

### Claim 4 (depends on 3)

The converter of claim 3, wherein the PDAC and the NDAC are alternately in:
a first coupling state in which the PDAC includes the first capacitor and a third capacitor and the NDAC includes the second capacitor and a fourth capacitor, and
a second coupling state in which the PDAC includes the fourth capacitor and the second capacitor and the NDAC includes the third capacitor and the first capacitor.

### Claim 5 (depends on 4)

The converter of claim 4, wherein the shuffle control circuity includes:
first analog signal routing circuitry to couple a positive version of a first analog signal to the third capacitor in the first coupling state and to couple an inverted version of a second analog signal to the third capacitor in the second coupling state.

### Claim 6 (depends on 5)

The converter of claim 5, wherein the shuffle control circuitry includes:
second analog signal routing circuitry to couple the positive version of the first analog signal to the fourth capacitor in the first coupling state and to couple the inverted version of the second analog signal to the fourth capacitor in the second coupling state, and
third analog signal routing circuitry to couple the positive version of the first analog signal to the second capacitor in the first coupling state and to couple the inverted version of the second analog signal to the second capacitor in the second coupling state.

### Claim 7 (depends on 4)

The converter of claim 4, wherein:
a capacitance value of the first capacitor substantially matches a capacitance value of the third capacitor; and
a capacitance value of the fourth capacitor substantially matches a capacitance value of the second capacitor.

### Claim 8 (depends on 1)

The converter of claim 1, wherein:
the PDAC includes a binary weighted capacitor array;
the NDAC includes a binary weighted capacitor array;
the PDAC and the NDAC are equivalent; and
the first capacitor includes one or more capacitors that together have a capacitance equal to approximately one-half of a total capacitance of the binary weighted capacitor array of the PDAC.

### Claim 9 (depends on 8)

The converter of claim 8 further comprising a second capacitor, second capacitor shuffled between a coupling of the second capacitor within the PDAC and a coupling of the second capacitor within the NDAC, wherein the second capacitor includes one or more capacitors that together have a capacitance equal to approximately one-half of a total capacitance of the binary weighted capacitor array of the NDAC.

### Claim 10

A method for reducing dielectric absorption of a successive approximation register analog to digital converter (SAR ADC) that includes a positive digital to analog converter (PDAC) and a negative digital to analog converter (NDAC), the method comprising:
selecting different analog signals from among multiple analog signals;
converting each analog signal that is selected from among the multiple analog signals to a sequence of digital code bits; and
shuffling a first capacitor between a coupling of the first capacitor within the PDAC and a coupling of the first capacitor within the NDAC after each conversion of the selected analog signal by the PDAC and NDAC.

### Claim 11 (depends on 10)

The method of claim 10, wherein the PDAC includes a binary weighted capacitor array, and wherein shuffling the first capacitor includes shuffling one or more capacitors that together have a capacitance equal to approximately one-half of a total capacitance of the binary weighted capacitor array of the PDAC.

### Claim 12 (depends on 10)

The method of claim 10, further including shuffling a second capacitor between a coupling of the second capacitor within the PDAC and a coupling of the second capacitor within the NDAC after each conversion, wherein shuffling the second capacitor includes shuffling one or more capacitors that together have a capacitance that is about one-half of a total capacitance of a binary weighted capacitor array that comprises the NDAC.

### Claim 13 (depends on 10)

The method of claim 10, wherein the PDAC and the NDAC are alternately in:
a first coupling state in which the PDAC includes the first capacitor and a third capacitor and the NDAC includes a second capacitor and a fourth capacitor, and
a second coupling state in which the PDAC includes the fourth capacitor and the second capacitor and the NDAC includes the third capacitor and the first capacitor.

### Claim 14 (depends on 13)

The method of claim 13 further comprising:
coupling a positive version of a first analog signal to the third capacitor in the first coupling state; and
coupling an inverted version of a second analog signal to the third capacitor in the second coupling state.

### Claim 15 (depends on 14)

The method of claim 14 further comprising:
coupling the positive version of the first analog signal to the fourth capacitor in the first coupling state;
coupling the inverted version of the second analog signal to the fourth capacitor in the second coupling state;
coupling the positive version of the first analog signal to the second capacitor in the first coupling state; and
coupling the inverted version of the second analog signal to the second capacitor in the second coupling state.

### Claim 16

An apparatus reducing dielectric absorption of a successive approximation register analog to digital converter (SAR ADC) that includes a positive digital to analog converter (PDAC) and a negative digital to analog converter (NDAC), the apparatus comprising:
means for selecting different analog signals from among multiple analog signals;
means for converting each analog signal selected from among the multiple analog signals to a sequence of digital code bits; and
means for shuffling a first capacitor between a coupling of the first capacitor within the PDAC and a coupling of the first capacitor within the NDAC after each conversion of the selected analog signal by the PDAC and NDAC.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein the PDAC includes a binary weighted capacitor array, and wherein means for shuffling the first capacitor includes means for shuffling one or more capacitors that together have a capacitance equal to approximately one-half of a total capacitance of the binary weighted capacitor array of the PDAC

### Claim 18 (depends on 16)

The apparatus of claim 16 further including means for shuffling a second capacitor between a coupling of the second capacitor within the PDAC and a coupling of the second capacitor within the NDAC after each conversion, wherein means for shuffling the second capacitor includes means for shuffling one or more capacitors that together have a capacitance that is about one-half of a total capacitance of a binary weighted capacitor array that comprises the NDAC.

### Claim 19 (depends on 16)

The apparatus of claim 16, wherein the PDAC and the NDAC are alternately in:
a first coupling state in which the PDAC includes the first capacitor and a third capacitor and the NDAC includes a second capacitor and a fourth capacitor, and
a second coupling state in which the PDAC includes the fourth capacitor and the second capacitor and the NDAC includes the third capacitor and the first capacitor.

### Claim 20 (depends on 16)

The apparatus of claim 16 further comprising:
means for coupling a positive version of a first analog signal to a third capacitor in a first coupling state;
means for coupling an inverted version of a second analog signal to the third capacitor in a second coupling state;
means for coupling the positive version of the first analog signal to a fourth capacitor in the first coupling state;
means for coupling the inverted version of the second analog signal to the fourth capacitor in the second coupling state;
means for coupling the positive version of the first analog signal to a second capacitor in the first coupling state; and
means for coupling the inverted version of the second analog signal to the second capacitor in the second coupling state.