# US 2019/0173477 A1 · Time-to-digital converter and digital phase locked loop > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0173477 A1 - Document ID: US20190173477A1 - Status: Published application - Kind: A1 - Application number: 16/256,477 - Filed: 2019-01-24 - Published: 2019-06-06 - Earliest claimed: 2016-05-17 - Assignees: Huawei Technologies Co., Ltd. - Applicants: Huawei Technologies Co., Ltd. - Inventors: Hao YAN; Jiale HUANG; Lei LU - Web page: https://patentgrep.com/patent/US20190173477A1 ## CPC - H03M 1/002: {Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed} - G04F 10/005: {Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60)} - H03L 7/0814: {the phase shifting device being digitally controlled} - H03M 1/502: {using tapped delay lines} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - G04F: TIME-INTERVAL MEASURING (measuring pulse characteristics G01R, e.g. G01R29/02; in radar or like systems G01S) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract A time-to-digital converter includes N stages of converting circuits, where N2, and N is an integer. Each stage of the converting circuit includes a first delayer and an arbiter; an output end of the first delayer in each stage of the converting circuit outputs a delayed signal of the stage of the converting circuit; and the arbiter in each stage of the converting circuit receives a sampling clock and the delayed signal of the stage of the converting circuit, and compares the sampling clock with the delayed signal to obtain an output signal of the stage of the converting circuit. The first delayer in each stage of the converting circuit includes at least one first delay cell circuit with a first time unit. The first delayer in any stage of the converting circuit includes a less number of first delay cell circuits than the first delayer in a next stage of the converting circuit. ## Claims ### Claim 1 A time-to-digital converter, comprising: N stages of converting circuits connected in series, wherein N2, and N is an integer; each stage of the converting circuits includes a first delayer and an arbiter, wherein a first delayer in a first stage of a converting circuit is configured to receive a reference signal, an input end of the first delayer in each stage of the converting circuit other than the first stage of the converting circuit is coupled to an output end of a first delayer in a previous stage of the converting circuit, and an output end of the first delayer in each stage of the converting circuit is configured to output a delayed signal of the each stage of the converting circuit; the arbiter in each stage of the converting circuit is configured to: receive a sampling clock of the each stage of the converting circuit and the delayed signal of the each stage of the converting circuit and compare the sampling clock with the delayed signal to obtain an output signal of the each stage of the converting circuit, wherein the sampling clock of the each stage of the converting circuit is derived from a clock signal; and the first delayer in the each stage of the converting circuit includes at least one first delay cell circuit, a delay time of each first delay cell circuit is a first time unit; and a quantity of first delay cell circuits included in the first delayer in any stage of the converting circuit is less than a quantity of first delay cell circuits included in the first delayer in a next stage of the converting circuit. ### Claim 2 (depends on 1) The time-to-digital converter according to claim 1, wherein a quantity of the first delay cell circuits is included in the first delayer in the first stage of the converting circuit is 1; and a quantity of the first delay cell circuits included in the first delayer in the each stage of the converting circuit other than the first stage of the converting circuit is less than a quantity of first delay cell circuits included in the first delayer in a next stage of the converting circuit. ### Claim 3 (depends on 2) The time-to-digital converter according to claim 2, wherein a quantity of the first delay cell circuits included in the first delayer in a jth converting circuit is 2j-2 time units, wherein j=2, 3 . . . N. ### Claim 4 (depends on 1) The time-to-digital converter according to claim 1, wherein the sampling clock of each stage of the converting circuit is the clock signal. ### Claim 5 (depends on 1) The time-to-digital converter according to claim 1, wherein the each stage of the converting circuit further includes a second delayer, wherein a second delayer in the first stage of the converting circuit is configured to receive the clock signal, an input end of the second delayer in the each stage of the converting circuit other than the first stage of the converting circuit is coupled to an output end of a second delayer in the previous stage of the converting circuit, and an output end of the second delayer in each stage of the converting circuit is configured to output the sampling clock of the stage of the converting circuit. ### Claim 6 (depends on 5) The time-to-digital converter according to claim 5, wherein the second delayer in each stage of the converting circuit includes at least one second delay cell circuit, a delay time of each second delay cell circuit is a second time unit; and a quantity of second delay cell circuits included in the second delayer in any stage of the converting circuit is less than a quantity of second delay cell circuits included in the second delayer in a next stage of the converting circuit. ### Claim 7 (depends on 6) The time-to-digital converter according to claim 6, wherein a quantity of the second delay cell circuits included in the second delayer in the first stage of the converting circuit is 1; and a quantity of the second delay cell circuits included in the second delayer in the each stage of the converting circuit other than the first stage of the converting circuit is less than a quantity of second delay cell circuits included in the second delayer in a next stage of the converting circuit. ### Claim 8 (depends on 7) The time-to-digital converter according to claim 7, wherein a quantity of the second delay cell circuits included in the second delayer in a jth converting circuit is 2j-2 time units, wherein j=2, 3 . . . N. ### Claim 9 (depends on 6) The time-to-digital converter according to claim 6, wherein the second time unit is less than the first time unit. ### Claim 10 (depends on 5) The time-to-digital converter according to claim 5, wherein the each stage of the converting circuit further includes a synchronization flip-flop; and the synchronization flip-flop in the each stage of the converting circuit is configured to sample an output signal generated in the stage of the converting circuit to synchronize the output signals of the N stages of converting circuits. ### Claim 11 (depends on 1) The time-to-digital converter according to claim 1, wherein in the N stages of the converting circuits, an arbiter in at least one stage of the converting circuit is an arbiter or a flip-flop. ### Claim 12 (depends on 11) The time-to-digital converter according to claim 11, wherein the flip-flop is a D flip-flop. ### Claim 13 A digital phase locked loop, comprising: a time-to-digital converter including N stages of converting circuits connected in series, wherein N2, and N is an integer; each stage of the converting circuits includes a first delayer and an arbiter, wherein a first delayer in a first stage of a converting circuit is configured to receive a reference signal, an input end of the first delayer in each stage of the converting circuit other than the first stage of the converting circuit is coupled to an output end of a first delayer in a previous stage of the converting circuit, and an output end of the first delayer in the each stage of the converting circuit is configured to output a delayed signal of the each stage of the converting circuit; the arbiter in the each stage of the converting circuit is configured to: receive a sampling clock of the each stage of the converting circuit and the delayed signal of the each stage of the converting circuit and compare the sampling clock with the delayed signal to obtain an output signal of the each stage of the converting circuit, wherein the sampling clock of the each stage of the converting circuit is derived from a clock signal; and the first delayer in the each stage of the converting circuit includes at least one first delay cell circuit, a delay time of each first delay cell circuit is a first time unit; and a quantity of first delay cell circuits included in the first delayer in any stage of the converting circuit is less than a quantity of first delay cell circuits included in the first delayer in a next stage of the converting circuit. ### Claim 14 (depends on 13) The digital phase locked loop according to claim 13, wherein a quantity of the first delay cell circuits included in the first delayer in the first stage of the converting circuit is 1; and a quantity of the first delay cell circuits included in the first delayer in the each stage of the converting circuit other than the first stage of the converting circuit is less than a quantity of first delay cell circuits included in the first delayer in a next stage of the converting circuit. ### Claim 15 (depends on 14) The digital phase locked loop according to claim 14, wherein a quantity of the first delay cell circuits included in the first delayer in a jth converting circuit is 2j-2 time units, wherein j=2, 3 . . . N. ### Claim 16 (depends on 13) The digital phase locked loop according to claim 13, wherein the each stage of the converting circuit further includes a second delayer, wherein a second delayer in the first stage of the converting circuit is configured to receive the clock signal, an input end of the second delayer in the each stage of the converting circuit other than the first stage of the converting circuit is coupled to an output end of a second delayer in the previous stage of the converting circuit, and an output end of the second delayer in the each stage of the converting circuit is configured to output the sampling clock of the stage of the converting circuit. ### Claim 17 (depends on 16) The digital phase locked loop according to claim 16, wherein the second delayer in the each stage of the converting circuit includes at least one second delay cell circuit, a delay time of the each second delay cell circuit is a second time unit; and a quantity of second delay cell circuits included in the second delayer in any stage of the converting circuit is less than a quantity of second delay cell circuits included in the second delayer in a next stage of the converting circuit. ### Claim 18 (depends on 17) The digital phase locked loop according to claim 17, wherein a quantity of the second delay cell circuits included in the second delayer in the first stage of the converting circuit is 1; and a quantity of the second delay cell circuits included in the second delayer in each stage of the converting circuit other than the first stage of the converting circuit is less than a quantity of second delay cell circuits included in the second delayer in a next stage of the converting circuit. ### Claim 19 (depends on 18) The digital phase locked loop according to claim 18, wherein a quantity of the second delay cell circuits included in the second delayer in a jth converting circuit is 2j-2 time units, wherein j=2, 3 . . . N. ### Claim 20 (depends on 17) The digital phase locked loop according to claim 17, wherein the second time unit is less than the first time unit.