Modulus divider with deterministic phase alignment
AssigneeIntegrated Device Technology, Inc.
InventorChengming He
Life of this patent
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Abstract
An apparatus includes a plurality of latches and a plurality of logic gates. Each latch may be setable and resettable. The logic gates may be connected to the latches to form a multi-modulus divider that generates an output clock signal by dividing an input clock signal in response to a command signal. Each latch may be commanded into a corresponding initial state while the command signal is in an initialization state. Each latch is generally free to change states while the command signal is in a run state. A modulus division operation of the multi-modulus divider may start upon an initial edge of the input clock signal after the command signal changes from the initialization state to the run state.
Claims20
An apparatus comprising:
- a plurality of latches each being setable and resettable;
- and
- a plurality of logic gates connected to said latches to form a multi-modulus divider that generates an output clock signal by dividing an input clock signal in response to a command signal, wherein (i) each of said latches is commanded into a corresponding initial state while said command signal is in an initialization state, (ii) each of said latches is free to change states while said command signal is in a run state and (iii) a modulus division operation of said multi-modulus divider starts upon an initial edge of said input clock signal after said command signal changes from said initialization state to said run state.
An apparatus comprising:
- a first circuit configured to (i) receive a command signal, an input clock signal and a feedback signal and (ii) generate an intermediate clock signal and an output clock signal;
- and
- a second circuit configured to (i) receive said command signal, said input clock signal and said intermediate clock signal and (ii) generate said feedback signal, wherein (a) each of a plurality of latches in both said first circuit and said second circuit is commanded into a corresponding initial state while said command signal is in an initialization state (b) each of said latches is free to change states while said command signal is in a running state and (c) a modulus division operation in each of said first circuit and said second circuit starts upon an initial edge of said input clock signal after said command signal changes from said initialization state to said run state.
Dependencies are inferred from the claim text.