# US 2019/0173440 A1 · Offset nulling for high-speed sense amplifier > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0173440 A1 - Document ID: US20190173440A1 - Status: Published application - Kind: A1 - Application number: 15/829,774 - Filed: 2017-12-01 - Published: 2019-06-06 - Earliest claimed: 2017-12-01 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Todd Morgan Rasmus; Minhan Chen - Web page: https://patentgrep.com/patent/US20190173440A1 ## CPC - H03F 3/45179: {using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence)} - H03F 3/45771: {using switching means} - H03F 2200/375: Circuitry to compensate the offset being present in an amplifier - H03F 2203/45042: One or more resistors are added or changed as balancing to reduce the offset of the dif amp - H03F 2203/45101: Control of the DC level being present - H03F 2203/45624: the LC comprising balancing means, e.g. trimming means - H03F 2203/45631: the LC comprising one or more capacitors, e.g. coupling capacitors - H03F 2203/45678: the LC comprising offset generating means - H03F 2203/45681: the LC comprising offset compensating means - H03F 2203/45726: the LC comprising more than one switch, which are not cross coupled - H03F: AMPLIFIERS ## Abstract A resistor in a pair of resistors is selectively coupled to a current source through a selection switch during the reset phase of a voltage-mode sense amplifier so that one evaluation node for the voltage-mode sense amplifier is discharged from a power supply voltage by an ohmic voltage drop across the selectively-coupled resistor to null an offset for the voltage-mode sense amplifier. ## Claims ### Claim 1 A voltage-mode sense amplifier, comprising: a differential pair of transistors; a pair of evaluation nodes, wherein the differential pair of transistors are configured to discharge, during an evaluation phase, one of the evaluation nodes faster than a remaining one of the evaluation nodes responsive to a binary value for a differential input signal; a current source; a pair of resistors corresponding to the pair of evaluation nodes on a one-to-one basis, wherein each resistor has a first terminal coupled to a power supply node and has a second terminal coupled to the corresponding evaluation node; a pair of switch transistors corresponding to the pair of resistors on a one-to-one basis, wherein each switch transistor is coupled between the second terminal of the corresponding resistor and the corresponding evaluation node, and wherein each switch transistor is configured to switch on during a reset phase and to switch off during the evaluation phase; and a selection switch configured to couple the current source to the second terminal of a selected one of the resistors to produce an ohmic voltage drop at the second terminal of the selected one of the resistors. ### Claim 2 (depends on 1) The voltage-mode sense amplifier of claim 1, further comprising a pair of cross-coupled inverters configured to latch a binary state for an output data signal responsive to a voltage difference between the pair of evaluation nodes during the evaluation phase. ### Claim 3 (depends on 1) The voltage-mode sense amplifier of claim 1, wherein a first one of the evaluation nodes is a drain for a first transistor in the differential pair of transistors, and wherein a second one of the evaluation nodes is a drain for a remaining second transistor in the differential pair of transistors. ### Claim 4 (depends on 1) The voltage-mode sense amplifier of claim 1, further comprising: a first capacitor, wherein a drain for a first transistor in the differential pair of transistors is coupled though the first capacitor to a first one of the evaluation nodes; and a second capacitor, wherein a drain for a remaining second transistor in the differential pair of transistors is coupled though the second capacitor to a remaining second one of the evaluation nodes. ### Claim 5 (depends on 1) The voltage-mode sense amplifier of claim 1, wherein the current source is a current digital-to-analog-converter. ### Claim 6 (depends on 1) The voltage-mode sense amplifier of claim 1, wherein the differential pair of transistors is an n-type metal oxide semiconductor (NMOS) differential pair of transistors. ### Claim 7 (depends on 2) The voltage-mode sense amplifier of claim 2, further comprising; a first n-type metal oxide semiconductor (NMOS) transistor coupled between ground and an output of a first one of the cross-coupled inverters, wherein a first evaluation node in the pair of evaluation nodes is coupled to a gate of the first NMOS transistor; and a second NMOS transistor coupled between ground and an output of a second one of the cross-coupled inverters, wherein a second evaluation node in the pair of evaluation nodes is coupled to a gate of the second NMOS transistor. ### Claim 8 (depends on 7) The voltage-mode sense amplifier of claim 7, further comprising at least one power switch configured between a power supply node and a power supply input node for each of the cross-coupled inverters, wherein the at least one power switch is configured to switch off during the reset phase and to switch on during the evaluation phase. ### Claim 9 (depends on 1) The voltage-mode sense amplifier of claim 1, further comprising: a first n-type metal oxide semiconductor (NMOS) transistor having a source connected to ground and a drain connected to a first transistor in the differential pair of transistors, wherein the first NMOS transistor is configured to switch on during the evaluation phase and to switch off during the reset phase; and a second NMOS transistor having a source connected to ground and a drain connected to a second transistor in the differential pair of transistors, wherein the second NMOS transistor is also configured to switch on during the evaluation phase and to switch off during the reset phase. ### Claim 10 (depends on 9) The voltage-mode sense amplifier of claim 9, wherein the switch transistors are p-type metal oxide (PMOS) transistors, and wherein a clock signal is configured to drive a gate for the first NMOS transistor, the second NMOS transistor, and for each of the switch transistors. ### Claim 11 A method of evaluating a differential data input signal in a voltage-mode sense amplifier, comprising: during a reset phase, charging a first evaluation node to a power supply voltage while charging a second evaluation node to the power supply voltage minus an ohmic voltage drop resulting from a current conducted through a resistor; during an evaluation phase following the reset phase, driving a differential pair of transistors with a differential input signal to discharge either the first evaluation node or the second evaluation node faster than a remaining one of the first evaluation node and the second evaluation node to produce an evaluation phase voltage difference between the first evaluation node and the second evaluation node responsive to a binary value for the differential input signal; and latching an output signal responsive to the voltage difference between the first evaluation node and the second evaluation node, wherein the voltage drop resulting from the current conducted through the resistor nulls an offset for the voltage-mode sense amplifier. ### Claim 12 (depends on 11) The method of claim 11, further comprising producing the current conducted through the resistor in a current digital-to-analog converter. ### Claim 13 (depends on 12) The method of claim 12, further comprising adjusting the current produced by the current digital-to-analog converter during a calibration phase so that the voltage-mode sense amplifier does not favor one binary state over another. ### Claim 14 (depends on 12) The method of claim 12, further comprising coupling the resistor to the current digital-to-analog converter through a selection switch. ### Claim 15 (depends on 11) The method of claim 11, wherein charging the first evaluation node to the power supply voltage also charges a drain for a first differential pair transistor in the differential pair of transistors to the power supply voltage, and wherein charging the second evaluation node to the power supply voltage minus the ohmic voltage drop also charges a drain for a second differential pair transistor in the differential pair of transistors to the power supply voltage minus the ohmic voltage drop. ### Claim 16 (depends on 11) The method of claim 11, further comprising: charging a pair of drains for the differential pair of transistors to the power supply voltage during the reset phase. ### Claim 17 A voltage-mode sense amplifier, comprising: a differential pair of transistors; a pair of evaluation nodes, wherein the differential pair of transistors are configured to discharge, during an evaluation phase, one of the evaluation node faster than a remaining one of the evaluation nodes responsive to a binary value for a differential input signal; a latch configured to latch a binary state for a data output signal during the evaluation phase responsive to a voltage difference between the pair of evaluation nodes; and means for charging a first evaluation node in the pair of evaluation nodes to a power supply voltage during a reset phase and to charge a second evaluation node in the pair of evaluation nodes to the power supply voltage minus an ohmic voltage drop during the reset phase. ### Claim 18 (depends on 17) The voltage-mode sense amplifier of claim 17, wherein the latch comprises a pair of cross-coupled inverters. ### Claim 19 (depends on 17) The voltage-mode sense amplifier of claim 17, further comprising: a first capacitor coupled between a gate of a first differential pair transistor in the differential pair of transistors and a drain of a second differential pair transistor in the differential pair of transistors; and a second capacitor coupled between a gate of the second differential pair transistor and a drain of the first differential pair transistor. ### Claim 20 (depends on 17) The voltage-mode sense amplifier of claim 17, wherein the differential pair of transistors is a differential pair of NMOS transistors.