# US 2019/0173437 A1 · Programmable filter in an amplifier > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0173437 A1 - Document ID: US20190173437A1 - Status: Published application - Kind: A1 - Application number: 16/268,552 - Filed: 2019-02-06 - Published: 2019-06-06 - Earliest claimed: 2014-09-16 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Rajendrakumar Joish - Web page: https://patentgrep.com/patent/US20190173437A1 ## CPC - H03F 3/19: with semiconductor devices only - G02B 27/017: {Head mounted} - G02B 27/0172: {characterised by optical features} - G06F 3/011: {Arrangements for interaction with the human body, e.g. for user immersion in virtual reality (blind teaching G09B21/00)} - G06F 3/017: {Gesture based interaction, e.g. based on a set of recognized hand gestures (interaction based on gestures traced on a digitiser G06F3/04883)} - G06T 19/006: {Mixed reality (object pose determination, tracking or camera calibration for mixed reality G06T7/00)} - H03F 1/0205: {in transistor amplifiers} - H03F 3/191: Tuned amplifiers (H03F3/193, H03F3/195 take precedence) - H03F 3/45098: {PI types (H03F3/45125, H03F3/45152 take precedence)} - H03F 3/45103: {Non-folded cascode stages} - G02B 2027/0112: {comprising device for genereting colour display} - G02B 2027/0138: {comprising image capture systems, e.g. camera} - G02B 2027/014: {comprising information/image processing systems} - G02B 2027/0187: {slaved to motion of at least a part of the body of the user, e.g. head, eye} - H03F 1/0277: {Selecting one or more amplifiers from a plurality of amplifiers} - H03F 1/22: by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively - H03F 1/223: {with MOSFET's} - H03F 1/3211: {in differential amplifiers} - H03F 3/45: Differential amplifiers (differential sense amplifiers G11C7/062) - H03F 2200/111: the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not - H03F 2200/294: the amplifier being a low noise amplifier [LNA] - H03F 2200/451: the amplifier being a radio frequency amplifier - H03F 2200/546: A tunable capacitance being present in an amplifier circuit - H03F 2203/45296: the AAC comprising one or more discrete capacitive elements, e.g. a transistor coupled as capacitor - H03F 2203/45396: the AAC comprising one or more switches - H03F: AMPLIFIERS - G02B: OPTICAL ELEMENTS, SYSTEMS OR APPARATUS - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ## Abstract The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input and generates a first load current. A first output node is coupled to a power supply through a first load resistor. The first load resistor receives the first load current. A first capacitor network is coupled to the first output node and draws a first capacitive current from the first output node. A first current buffer is coupled between the first output node and the first transistor. A current through the first current buffer is a summation of the first load current and the first capacitive current. ## Claims ### Claim 1 An amplifier comprising: a first transistor configured to receive a first input and configured to generate a first load current; a first output node coupled to a power supply through a first load resistor, the first load resistor configured to receive the first load current; a first capacitor network coupled to the first output node and configured to draw a first capacitive current from the first output node; and a first current buffer coupled between the first output node and the first transistor, wherein a current through the first current buffer is a summation of the first load current and the first capacitive current. ### Claim 2 (depends on 1) The amplifier of claim 1 further comprising: a second transistor configured to receive a second input and configured to generate a second load current; a second output node coupled to a power supply through a second load resistor, the second load resistor configured to receive the second load current; a second capacitor network coupled to the second output node and configured to draw a second capacitive current from the second output node; and a second current buffer coupled between the second output node and the second transistor, wherein a current through the second current buffer is a summation of the second load current and the second capacitive current. ### Claim 3 (depends on 1) The amplifier of claim 1, wherein the first current buffer is a BJT cascode transistor whose base terminal is coupled to a first bias voltage, whose collector terminal is coupled to the first output node, and whose emitter terminal is coupled to the first transistor. ### Claim 4 (depends on 2) The amplifier of claim 2, wherein the second current buffer is a BJT cascode transistor whose base terminal is coupled to a second bias voltage, whose collector terminal is coupled to the second output node, and whose emitter terminal is coupled to the second transistor. ### Claim 5 (depends on 1) The amplifier of claim 1 further comprising a filter network, wherein the filter network comprises: the first capacitor network coupled in parallel to the first current buffer; the second capacitor network coupled in parallel to the second current buffer; and a primary switch coupled between the first capacitor network and the second capacitor network. ### Claim 6 (depends on 1) The amplifier of claim 1, wherein when the primary switch is inactivated: the first switch and the second switch are activated; the first capacitive current flows through the first capacitor and the first switch; and the second capacitive current flows through the second capacitor and the second switch. ### Claim 7 (depends on 1) The amplifier of claim 1 further comprising a first fixed capacitor coupled between the first output node and a ground terminal, and a second fixed capacitor coupled between the second output node and the ground terminal. ### Claim 8 (depends on 1) The amplifier of claim 1 further comprising: an impedance coupled between the first transistor and the second transistor; a first biasing current source coupled between the first transistor and the ground terminal; and a second biasing current source coupled between the second transistor and the ground terminal. ### Claim 9 A method comprising: inactivating a primary switch; generating a first load current in response to a first input, the first load current received by a first load resistor; providing a first capacitive current to a first capacitor network; and providing a current that is a summation of the first load current and the first capacitive current to a first current buffer, the first current buffer coupled in parallel to the first capacitor network. ### Claim 10 (depends on 9) The method of claim 9 further comprising: generating a second load current in response to a second input, the second load current received by a second load resistor; providing the second capacitive current to a second capacitor network; and providing a current that is a summation of the second load current and the second capacitive current to a second current buffer, the second current buffer coupled in parallel to the second capacitor network. ### Claim 11 (depends on 9) The method of claim 9, wherein providing the first capacitive current to the first capacitor network further comprises activating a first switch in the first capacitor network, and providing the second capacitive current to the second capacitor network further comprises activating a second switch in the second capacitor network, wherein the primary switch is coupled in between the first switch and the second switch. ### Claim 12 (depends on 9) The method of claim 9 further comprising generating the first load current by a first transistor in response to the first input, and generating the second load current by a second transistor in response to the second input. ### Claim 13 An amplifier comprising: a first output node coupled to a power supply through a first load resistor; a second output node coupled to the power supply through a second load resistor; a first current buffer coupled to the first output node; a second current buffer coupled to the second output node; a filter network coupled between the first output node and the second output node, the filter network comprising: a first capacitor network coupled between the first output node and the second current buffer; a second capacitor network coupled between the second output node and the first current buffer; and a primary switch coupled between the first capacitor network and the second capacitor network.