# US 2019/0173430 A1 · Multiple-path amplifier with series component along inverter between amplifier outputs > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0173430 A1 - Document ID: US20190173430A1 - Status: Published application - Kind: A1 - Application number: 15/830,477 - Filed: 2017-12-04 - Published: 2019-06-06 - Earliest claimed: 2017-12-04 - Assignees: NXP USA, Inc. - Applicants: NXP USA, Inc. - Inventors: James Krehbiel; Nick Yang; Joseph Gerard Schultz; Enver Krvavac; Yu-Ting David Wu - Web page: https://patentgrep.com/patent/US20190173430A1 ## CPC - H03F 1/0288: {using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers} - H03F 1/565: {using inductive elements} - H03F 3/189: High-frequency amplifiers, e.g. radio frequency amplifiers - H03F 3/195: in integrated circuits - H03F 3/24: of transmitter output stages - H03F 3/605: {Distributed amplifiers} - H10W 44/20: at high-frequency [HF] or radio frequency [RF] - H03F 2200/222: A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier - H03F 2200/318: A matching circuit being used as coupling element between two amplifying stages - H03F 2200/387: A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier - H03F 2200/411: the output amplifying stage of an amplifier comprising two power stages - H03F 2200/432: Two or more amplifiers of different type are coupled in parallel at the input or output, e.g. a class D and a linear amplifier, a class B and a class A amplifier - H03F 2200/451: the amplifier being a radio frequency amplifier - H10W 44/206: {Wires} - H10W 44/234: {Arrangements for impedance matching} - H10W 44/251: {for monolithic microwave integrated circuits [MMIC]} - H03F: AMPLIFIERS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Embodiments of a multiple-path amplifier (e.g., a Doherty amplifier) and a module housing the amplifier include a first amplifier (or first power transistor die) with a first output terminal, a second amplifier (or second power transistor die) with a second output terminal, and an impedance inverter line assembly electrically connected between the first and second output terminals. The impedance inverter line assembly includes a first transmission line and a surface mount component connected in series between the first and second output terminals. In various embodiments, the surface mount component is selected from a fixed-value capacitor, a fixed-value inductor, a tunable capacitor, a tunable inductor, and a tunable passive component network. ## Claims ### Claim 1 A multiple-path amplifier comprising: a first amplifier with a first output terminal; a second amplifier with a second output terminal; and an impedance inverter line assembly electrically connected between the first and second output terminals, wherein the impedance inverter line assembly includes a first transmission line and a surface mount component connected in series between the first and second output terminals, wherein the surface mount component is selected from a fixed-value capacitor, a fixed-value inductor, a tunable capacitor, a tunable inductor, and a tunable passive component network. ### Claim 2 (depends on 1) The multiple-path amplifier of claim 1, wherein the multiple-path amplifier is a Doherty amplifier, the first amplifier is a carrier amplifier, and the second amplifier is a peaking amplifier. ### Claim 3 (depends on 1) The multiple-path amplifier of claim 1, wherein the impedance inverter line assembly further comprises: a second transmission line, wherein a first end of the first transmission line is coupled to the first output, a second end of the first transmission line is coupled to a first terminal of the surface mount component, a first end of the second transmission line is coupled to a second terminal of the surface mount component, and a second end of the second transmission line is coupled to the second output. ### Claim 4 (depends on 3) The multiple-path amplifier of claim 3, wherein the impedance inverter line assembly further comprises: a first connector electrically coupled between the first output and the first end of the first transmission line; and a second connector electrically coupled between the second output and the second end of the second transmission line. ### Claim 5 (depends on 4) The multiple-path amplifier of claim 4, wherein: the first connector comprises a first wirebond array; and the second connector comprises a second wirebond array. ### Claim 6 (depends on 1) The multiple-path amplifier of claim 1, wherein the surface mount component is a surface mount capacitor. ### Claim 7 (depends on 6) The multiple-path amplifier of claim 6, wherein the capacitor has a capacitance value in a range from 3.0 picofarads to 33 picofarads. ### Claim 8 (depends on 1) The multiple-path amplifier of claim 1, wherein the surface mount component is a surface mount inductor. ### Claim 9 (depends on 8) The multiple-path amplifier of claim 8, wherein the inductor has an inductance value in a range from 0.3 nanohenries to 4.4 nanohenries. ### Claim 10 (depends on 1) The multiple-path amplifier of claim 1, wherein the surface mount component includes a substrate to which a passive electrical component is coupled. ### Claim 11 (canceled) ### Claim 12 A multiple-path amplifier comprising: a first amplifier with a first output terminal; a second amplifier with a second output terminal; and an impedance inverter line assembly electrically connected between the first and second output terminals, wherein the impedance inverter line assembly includes a first transmission line and a surface mount component connected in series between the first and second output terminals, wherein the first output terminal corresponds to a first intrinsic drain of a first power transistor with a first drain-source capacitance, the second output terminal corresponds to a second intrinsic drain of a second power transistor with a second drain-source capacitance, and the impedance inverter line assembly and the first and second drain-source capacitances provide an impedance inversion and a 90 degree phase difference between the first intrinsic drain to the second intrinsic drain. ### Claim 13 An amplifier comprising: a first substrate with a mounting surface; a first power transistor die coupled to the mounting surface, wherein the first power transistor die includes a first transistor integrated within the first power transistor die, and wherein the first transistor includes a first drain terminal; a second power transistor die coupled to the mounting surface, wherein the second power transistor die includes a second transistor integrated within the second power transistor die, and wherein the second transistor includes a second drain terminal; and an impedance inverter line assembly electrically connected between the first and second output terminals, wherein the impedance inverter line assembly includes a first transmission line and a surface mount component connected in series between the first and second output terminals, wherein the surface mount component is selected from a surface mount capacitor, a surface mount inductor, and a second substrate to which a passive electrical component is coupled. ### Claim 14 (depends on 13) The amplifier of claim 13, wherein the amplifier is a Doherty amplifier, the first transistor forms a portion of a carrier amplifier, and the second transistor forms a portion of a peaking amplifier. ### Claim 15 (depends on 13) The amplifier of claim 13, wherein the impedance inverter line assembly further comprises: a second transmission line, wherein a first end of the first transmission line is coupled to the first output, a second end of the first transmission line is coupled to a first terminal of the surface mount component, a first end of the second transmission line is coupled to a second terminal of the surface mount component, and a second end of the second transmission line is coupled to the second output. ### Claim 16 (depends on 15) The amplifier of claim 15, wherein the impedance inverter line assembly further comprises: a first wirebond array electrically coupled between the first output and the first end of the first transmission line; and a second wirebond array electrically coupled between the second output and the second end of the second transmission line. ### Claim 17 (canceled) ### Claim 18 An amplifier comprising: a first substrate with a mounting surface; a first power transistor die coupled to the mounting surface, wherein the first power transistor die includes a first transistor integrated within the first power transistor die, and wherein the first transistor includes a first drain terminal; a second power transistor die coupled to the mounting surface, wherein the second power transistor die includes a second transistor integrated within the second power transistor die, and wherein the second transistor includes a second drain terminal; and an impedance inverter line assembly electrically connected between the first and second output terminals, wherein the impedance inverter line assembly includes a first transmission line and a surface mount component connected in series between the first and second output terminals, wherein the surface mount component is selected from a fixed-value capacitor, a fixed-value inductor, a tunable capacitor, a tunable inductor, and a tunable passive component network. ### Claim 19 A module that houses at least a portion of a Doherty amplifier, the module comprising: a first substrate with a mounting surface; a carrier amplifier die connected to the mounting surface, wherein the carrier amplifier die includes a first transistor integrated within the carrier amplifier die, and wherein the first transistor includes a first drain terminal; a peaking amplifier die connected to the mounting surface, wherein the peaking amplifier die includes a second transistor integrated within the peaking amplifier die, and wherein the second transistor includes a second drain terminal; and an impedance inverter line assembly electrically connected between the first and second output terminals, wherein the impedance inverter line assembly includes a first transmission line connected to the mounting surface, and a surface mount component connected to the mounting surface in series between the first and second output terminals, wherein the surface mount component is selected from a fixed-value capacitor, a fixed-value inductor, a tunable capacitor, a tunable inductor, and a tunable passive component network. ### Claim 20 (depends on 19) The module of claim 19, wherein the impedance inverter line assembly further comprises: a second transmission line connected to the mounting surface, wherein a first end of the first transmission line is coupled to the first output, a second end of the first transmission line is coupled to a first terminal of the surface mount component, a first end of the second transmission line is coupled to a second terminal of the surface mount component, and a second end of the second transmission line is coupled to the second output. ### Claim 21 (depends on 19) The module of claim 19, wherein the Doherty amplifier is a 90-0 Doherty amplifier, and an electrical distance between intrinsic drains of the first and second transistors is 90 degrees. ### Claim 22 (depends on 19) The module of claim 19, wherein the Doherty amplifier is a 270-90 Doherty amplifier, and an electrical distance between intrinsic drains of the first and second transistors is 270 degrees. ### Claim 23 (canceled)