# US 2019/0173389 A1 · Active cmos recovery units for wireless power transmission

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- Number: US 2019/0173389 A1
- Document ID: US20190173389A1
- Status: Published application
- Kind: A1
- Application number: 16/004,198
- Filed: 2018-06-08
- Published: 2019-06-06
- Earliest claimed: 2013-11-22
- Assignees: California Institute of Technology
- Applicants: California Institute of Technology
- Inventors: Seyed Ali Hajimiri; Behrooz Abiri; Florian Bohn
- Web page: https://patentgrep.com/patent/US20190173389A1

## CPC

- H02M 7/217: using semiconductor devices only
- H02J 4/25: for transfer of electric power between AC and DC networks, e.g. for supplying the DC section within a load from an AC mains system
- H02J 50/005: {Mechanical details of housing or structure aiming to accommodate the power transfer means, e.g. mechanical integration of coils, antennas or transducers into emitting or receiving devices}
- H02J 50/27: characterised by the type of receiving antennas, e.g. rectennas
- H02J 50/10: using inductive coupling
- H02M 1/123: {Suppression of common mode voltage or current}
- H02M 7/003: {Constructional details, e.g. physical layout, assembly, wiring or busbar connections}
- H02M 7/23: arranged for operation in parallel {(H02M7/2176 takes precedence)}
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- H02J: ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY

## Abstract

A rectifying circuit includes, in part, first and second NMOS transistors, an impedance matching network, and an RF block circuit. The source and gate terminals of the first NMOS transistor respectively receive the ground potential and a biasing voltage. The second NMOS transistor has a gate terminal coupled to the drain terminal of the first NMOS transistor, a drain terminal coupled to the gate terminal of the first NMOS transistor, and a source terminal receiving the ground potential. The impedance matching network is disposed between the antenna and the drain terminals of the first and second NMOS transistors. The RF block circuit is coupled between the drain terminals of the first and second NMOS transistors and the output terminal of the rectifying circuit. The RF block circuit is adapted to prevent the RF signal from flowing into the output terminal of the rectifying circuit.

## Claims

### Claim at position 1

1-33. (canceled)

### Claim 34

A rectifying circuit adapted to rectify an RF signal supplied by an antenna, the rectifying circuit comprising:
a first MOS transistor having a source terminal receiving a ground voltage and a gate terminal receiving a biasing voltage;
a second MOS transistor having a source terminal receiving the ground voltage and a gate terminal receiving the biasing voltage, wherein a gate terminal of the first MOS transistor is coupled to a drain terminal of the second MOS transistor, and a gate terminal of the second MOS transistor is coupled to a drain terminal of the first MOS transistor;
a first inductive element coupled between an output terminal of the rectifying circuit and the drain terminal of the first MOS transistor;
s second inductive element coupled between the output terminal and the drain terminal of the second MOS transistor; and
a first capacitive element coupled between the output terminal and a ground terminal supplying the ground voltage.

### Claim 35 (depends on 34)

The rectifying circuit of claim 34 further comprising:
a second capacitive element disposed between the gate terminal of the first MOS transistor and the drain terminal of the second MOS transistor; and
a third capacitive element disposed between the gate terminal of the second MOS transistor and the drain terminal of the first MOS transistor.

### Claim 36 (depends on 34)

The rectifying circuit of claim 34 further comprising:
a biasing circuit supplying the biasing voltage to the gate terminals of the first and second MOS transistors.

### Claim 37 (depends on 34)

The rectifying circuit of claim 34 wherein said biasing circuit supplies a fixed voltage.

### Claim 38 (depends on 34)

The rectifying circuit of claim 34 wherein said biasing circuit supplies the biasing voltage in response to an output voltage sensed at the output terminal.

### Claim 39 (depends on 34)

The rectifying circuit of claim 34 wherein said rectifying circuit further comprises:
a first resistive element disposed between the biasing circuit and the gate terminal of the first MOS transistor; and
a second resistive element disposed between the biasing circuit and the gate terminal of the second MOS transistor.

### Claim 40 (depends on 34)

The rectifying circuit of claim 34 wherein said RF signal is applied between the drain terminals of the first and second MOS transistors.

### Claim 41 (depends on 34)

The rectifying circuit of claim 34 wherein said RF signal is applied between the drain terminal of one of the first or second MOS transistors and the ground terminal.

### Claim 42 (depends on 34)

The rectifying circuit of claim 34 wherein said rectifying circuit further comprises:
a third inductive element disposed between the biasing circuit and the gate terminal of the first MOS transistor; and
a fourth inductive element disposed between the biasing circuit and the gate terminal of the second MOS transistor.

### Claim 43

A method of rectifying an RF signal delivered by an antenna, the method comprising:
applying a biasing voltage to a gate terminal of a first MOS transistor having a source terminal receiving a ground potential;
applying the biasing voltage to a gate terminal of a second MOS transistor, wherein the gate terminal of the first MOS transistor is coupled to a drain terminal of the second MOS transistor, and the gate terminal of the second MOS transistor is coupled to a drain terminal of the first MOS transistor, and wherein a source terminal of the second MOS transistor receives the ground potential;
coupling a first inductive element between an output terminal supplying the rectified signal and the drain terminal of the first MOS transistor;
coupling a second inductive element between the output terminal and the drain terminal of the second MOS transistor; and
coupling a capacitive element between the output terminal and the ground terminal.

### Claim 44 (depends on 43)

The method of claim 43 further comprising:
supplying the biasing voltage to the gate terminal of the first MOS transistor via a second capacitive element; and
supplying the biasing voltage to the gate terminal of the second MOS transistor via a third capacitive element.

### Claim 45 (depends on 43)

The method of claim 43 further comprising:
supplying the biasing voltage via a fixed voltage supply.

### Claim 46 (depends on 43)

The method of claim 43 further comprising:
supplying the biasing voltage in response to a voltage sensed at the output terminal.

### Claim 47 (depends on 43)

The method of claim 43 further comprising:
applying the RF signal between the drain terminals of the first and second MOS transistors.

### Claim 48 (depends on 43)

The method of claim 43 further comprising:
applying the RF signal between the drain terminal of one of the first or second MOS transistors and the ground terminal.

### Claim 49 (depends on 43)

The method of claim 43 further comprising:
coupling a third inductive element between the gate terminal of the first MOS transistor and the biasing circuit; and
coupling a fourth inductive element between the gate terminal of the second MOS transistor and the biasing circuit.