# US 2019/0172954 A1 · Top-gate self-aligned metal oxide semiconductor tft and method of making the same

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- Number: US 2019/0172954 A1
- Document ID: US20190172954A1
- Status: Published application
- Kind: A1
- Application number: 15/736,132
- Filed: 2017-11-20
- Published: 2019-06-06
- Earliest claimed: 2017-10-09
- Assignees: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
- Applicants: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
- Inventors: Xingyu ZHOU; Jangsoon IM
- Web page: https://patentgrep.com/patent/US20190172954A1

## CPC

- H10D 64/01: Manufacture or treatment
- H10D 30/6723: {having light shields}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/80: characterised by the materials
- H10D 64/011: {of electrodes ohmically coupled to a semiconductor}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10K 59/12: Active-matrix OLED [AMOLED] displays
- H10K 59/125: including organic TFTs [OTFT]
- H10K 59/126: Shielding, e.g. light-blocking means over the TFTs
- H10K 59/8791: {Arrangements for improving contrast, e.g. preventing reflection of ambient light}
- H10P 76/204: {of organic photoresist masks}
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10K 59/131: Interconnections, e.g. wiring lines or terminals
- H10P 50/20: Dry etching; Plasma etching; Reactive-ion etching
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P 95/70: Chemical treatments
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a top-gate self-aligned metal oxide semiconductor TFT and a manufacturing method thereof. By providing a light-shielding layer below an active layer to protect the active layer from light irradiation and prevent the TFT from generating a negative threshold voltage drift phenomenon. Further, by connecting the light-shielding layer to the source, a stable voltage is generated on the light-shielding layer to avoid the floating gate effect, so as to improve the working stability of the TFT effectively. The top-gate self-aligned metal oxide semiconductor TFT produced by the method of the present disclosure does not generate negative threshold voltage drift phenomenon and floating gate effect, resulting in good working stability.

## Claims

### Claim 1

A method of manufacturing a top-gate self-aligned metal oxide semiconductor TFT, wherein a light-shielding layer is provided below an active layer, and the light-shielding layer is connected to a source.

### Claim 2 (depends on 1)

The method of manufacturing a top-gate self-aligned metal oxide semiconductor TFT according to claim 1, comprising:
providing a base substrate, forming the light-shielding layer on the base substrate, forming a buffer layer on the base substrate covering the light-shielding layer, forming the active layer on the buffer layer corresponding to a region above the light-shielding layer, a material of the active layer is a metal oxide semiconductor material;
forming a gate insulating layer on the buffer layer covering the active layer, and depositing a gate metal layer on the gate insulating layer;
forming a photoresist layer on the gate metal layer and patterning the photoresist layer by a photo lithography process, wherein the remaining photoresist layer defines a gate pattern on the gate metal layer;
using the photoresist layer as a barrier and etching the gate metal layer to obtain a gate corresponding to a region above the active layer;
using the photoresist layer and the gate as the barrier, etching the gate insulating layer by keeping only a portion corresponding to a region below the gate and removing other portions, wherein the keeping gate insulating layer is located on the active layer and aligned with the gate from top to bottom, the gate and the gate insulating layer define a channel region corresponding to a region below the gate insulating layer, as well as a source contact region and a drain contact region located on two sides of the channel region, respectively;
using the photoresist layer, the gate and the gate insulating layer as the barrier, conducting a conductive treatment on the active layer, turning the metal oxide semiconductor material of the source contact region and the drain contact region into a conductor, keeping semiconductor characteristics for the metal oxide semiconductor material of the channel region; and peeling off the photoresist layer after the conductive treatment is completed;
forming an interlayer insulating layer on the buffer layer covering the gate and the active layer; forming a source contact hole and a drain contact hole on the interlayer insulating layer corresponding respectively to the source contact region and the drain contact region, and simultaneously forming a signal via hole on the interlayer insulating layer and the buffer layer corresponding to a region above the light shielding layer;
forming the source and a drain on the interlayer insulating layer, wherein the source and the drain are respectively electrically connected to the source contact region and the drain contact region through the source contact hole and the drain contact hole, while the source is electrically connected to the light-shielding layer through the signal via hole; and
forming a passivation layer on the interlayer insulating layer covering the source and the drain.

### Claim 3 (depends on 2)

The method of manufacturing a top-gate self-aligned metal oxide semiconductor TFT according to claim 2, wherein the method of conducting a conductive treatment on the active layer is a plasma treatment for reducing oxygen content of the metal oxide semiconductor material, so as to reduce the resistivity of the metal oxide semiconductor material, and turn the metal oxide semiconductor material into a conductor.

### Claim 4 (depends on 3)

The method of manufacturing a top-gate self-aligned metal oxide semiconductor TFT according to claim 3, wherein the plasma comprises one or more of helium plasma, argon plasma, and ammonia plasma.

### Claim 5 (depends on 2)

The method of manufacturing a top-gate self-aligned metal oxide semiconductor TFT according to claim 2, wherein an area of the light-shielding layer is greater than that of the active layer, and an orthographic projection of the light-shielding layer on the base substrate covers the orthographic projection of the active layer on the base substrate; a thickness of the active layer is 100 Å-1000 Å, and the metal oxide semiconductor material includes one or more of indium-gallium-zinc-oxide, indium-zinc-tin-oxide, and indium-gallium-zinc-tin-oxide.

### Claim 6 (depends on 5)

The method of manufacturing a top-gate self-aligned metal oxide semiconductor TFT according to claim 5, wherein when the metal oxide semiconductor material is indium-gallium-zinc-oxide, and after conducting the conductive treatment on the source contact region and the drain contact region of the active layer, a molar ratio of indium, gallium, zinc and oxygen in the indium-gallium-zinc-oxide of the source contact region and the drain contact region of the active layer is, In:Ga:Zn:O=1:1:1:X2, where X2 is less than 1, and the molar ratio of indium, gallium, zinc and oxygen in the indium-gallium-zinc-oxide of the channel region of the active layer is, In:Ga:Zn:O=1:1:1:X1, where X1 is between 1 and 10.

### Claim 7

A top-gate self-aligned metal oxide semiconductor TFT comprising: an active layer, a light-shielding layer provided below the active layer, and a source connected to the light-shielding layer.

### Claim 8 (depends on 7)

The top gate self-aligned metal oxide semiconductor TFT according to claim 7, further comprising: a base substrate, a light-shielding layer disposed on the base substrate, a buffer layer disposed on the base substrate covering the light-shielding layer, an active layer disposed on the buffer layer corresponding to a region above the light-shielding layer, a gate insulating layer disposed on the active layer, a gate disposed on the gate insulting layer aligning with the gate insulting layer, an interlayer insulating layer disposed on the buffer layer covering the gate and the active layer, a source and a drain disposed on the interlayer insulating layer, and a passivation layer disposed on the interlayer insulating layer covering the source and the drain;
the active layer comprises a channel region corresponding to a region below the gate insulating layer, a source contact region and drain contact region respectively located at two sides of the channel region; a material of the source contact region and the drain contact region is a conductive metal oxide semiconductor material, a material of the channel region is a metal oxide semiconductor material having semiconductor properties;
a source contact hole and a drain contact hole are disposed on the interlayer insulating layer corresponding to the source contact region and the drain contact region, respectively, a signal via hole is disposed on the interlayer insulating layer and the buffer layer corresponding to a region above the light-shielding layer; and
the source and the drain are respectively electrically connected to the source contact region and the drain contact region of the active layer through the source contact hole and the drain contact hole, while the source is electrically connected to the light-shielding layer through the signal via hole.

### Claim 9 (depends on 8)

The top gate self-aligned metal oxide semiconductor TFT according to claim 8, wherein an area of the light-shielding layer is greater than that of the active layer, and an orthographic projection of the light-shielding layer on the base substrate covers the orthographic projection of the active layer on the base substrate; a thickness of the active layer is 100 Å-1000 Å, and the metal oxide semiconductor material includes one or more of indium-gallium-zinc-oxide, indium-zinc-tin-oxide, and indium-gallium-zinc-tin-oxide.

### Claim 10 (depends on 9)

The top gate self-aligned metal oxide semiconductor TFT according to claim 9, wherein when the metal oxide semiconductor material is indium-gallium-zinc-oxide, a molar ratio of indium, gallium, zinc and oxygen in the indium-gallium-zinc-oxide of the source contact region and the drain contact region of the active layer is, In:Ga:Zn:O=1:1:1:X2, where X2 is less than 1, and the molar ratio of indium, gallium, zinc and oxygen in the indium-gallium-zinc-oxide of the channel region of the active layer is, In:Ga:Zn:O=1:1:1:X1, where X1 is between 1 and 10.

### Claim 11

A method of manufacturing a top-gate self-aligned metal oxide semiconductor TFT, comprising providing a light-shielding layer below an active layer, and connecting the light-shielding layer to a source; the method further comprising:
providing a base substrate, forming the light-shielding layer on the base substrate, forming a buffer layer on the base substrate covering the light-shielding layer, forming the active layer on the buffer layer corresponding to a region above the light-shielding layer, a material of the active layer is a metal oxide semiconductor material;
forming a gate insulating layer on the buffer layer covering the active layer, and depositing a gate metal layer on the gate insulating layer;
forming a photoresist layer on the gate metal layer and patterning the photoresist layer by a photo lithography process, wherein the remaining photoresist layer defines a gate pattern on the gate metal layer;
using the photoresist layer as a barrier and etching the gate metal layer to obtain a gate corresponding to a region above the active layer;
using the photoresist layer and the gate as the barrier, etching the gate insulating layer by keeping only a portion corresponding to a region below the gate and removing other portions, wherein the keeping gate insulating layer is located on the active layer and aligned with the gate from top to bottom, the gate and the gate insulating layer define a channel region corresponding to a region below the gate insulating layer, as well as a source contact region and a drain contact region located on two sides of the channel region, respectively;
using the photoresist layer, the gate and the gate insulating layer as the barrier, conducting a conductive treatment on the active layer, turning the metal oxide semiconductor material of the source contact region and the drain contact region into a conductor, keeping semiconductor characteristics for the metal oxide semiconductor material of the channel region; and peeling off the photoresist layer after the conductive treatment is completed;
forming an interlayer insulating layer on the buffer layer covering the gate and the active layer; forming a source contact hole and a drain contact hole on the interlayer insulating layer corresponding respectively to the source contact region and the drain contact region, and simultaneously forming a signal via hole on the interlayer insulating layer and the buffer layer corresponding to a region above the light shielding layer,
forming the source and a drain on the interlayer insulating layer, wherein the source and the drain are respectively electrically connected to the source contact region and the drain contact region through the source contact hole and the drain contact hole, while the source is electrically connected to the light-shielding layer through the signal via hole;
forming a passivation layer on the interlayer insulating layer covering the source and the drain;
wherein the method of conducting a conductive treatment on the active layer is a plasma treatment for reducing oxygen content of the metal oxide semiconductor material, so as to reduce the resistivity of the metal oxide semiconductor material, and turn the metal oxide semiconductor material into a conductor,
wherein the plasma comprises one or more of helium plasma, argon plasma, and ammonia plasma; and
wherein an area of the light-shielding layer is greater than that of the active layer, and an orthographic projection of the light-shielding layer on the base substrate covers the orthographic projection of the active layer on the base substrate; a thickness of the active layer is 100 Å-1000 Å, and the metal oxide semiconductor material includes one or more of indium-gallium-zinc-oxide, indium-zinc-tin-oxide, and indium-gallium-zinc-tin-oxide.

### Claim 12 (depends on 11)

The method of manufacturing a top-gate self-aligned metal oxide semiconductor TFT according to claim 11, wherein when the metal oxide semiconductor material is indium-gallium-zinc-oxide, and after conducting the conductive treatment on the source contact region and the drain contact region of the active layer, a molar ratio of indium, gallium, zinc and oxygen in the indium-gallium-zinc-oxide of the source contact region and the drain contact region of the active layer is, In:Ga:Zn:O=1:1:1:X2, where X2 is less than 1, and the molar ratio of indium, gallium, zinc and oxygen in the indium-gallium-zinc-oxide of the channel region of the active layer is, In:Ga:Zn:O=1:1:1:X1, where X1 is between 1 and 10.