# US 2019/0172953 A1 · Thin film transistor, manufacturing method, array substrate, display panel, and device

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- Number: US 2019/0172953 A1
- Document ID: US20190172953A1
- Status: Published application
- Kind: A1
- Application number: 15/992,909
- Filed: 2018-05-30
- Published: 2019-06-06
- Earliest claimed: 2017-12-06
- Assignees: Boe Technology Group Co., Ltd.; Hefei Xinsheng Optoelectronics Technology Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.; Hefei Xinsheng Optoelectronics Technology Co., Ltd
- Inventors: Yuankui DING; Ce ZHAO; Guangcai YUAN; Yingbin HU; Leilei CHENG; Jun CHENG; Bin ZHOU
- Web page: https://patentgrep.com/patent/US20190172953A1

## CPC

- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present disclosure discloses a TFT, a manufacturing method, an array substrate, a display panel, and a device. The TFT includes a hydrogen-containing buffer layer located on a substrate; an oxide semiconductor layer located on the buffer layer, wherein the oxide semiconductor layer includes a conductor region and a semiconductor region; a source or drain located on the conductor region, and electrically connected to the conductor region; and a gate structure located on the semiconductor region.

## Claims

### Claim 1

A thin film transistor, comprising:
a substrate;
a hydrogen-containing buffer layer, located on the substrate;
an oxide semiconductor layer, located on the buffer layer, comprising a conductor region and a semiconductor region;
a source or drain, located on the conductor region, and electrically connected to the conductor region; and
a gate structure, located on the semiconductor region.

### Claim 2 (depends on 1)

The TFT according to claim 1, further comprising:
a blocking layer, located between the buffer layer and the semiconductor region, and configured to block hydrogen in the buffer layer from entering into the semiconductor region.

### Claim 3 (depends on 1)

The TFT according to claim 1, wherein the hydrogen-containing buffer layer comprises a first hydrogen-containing region corresponding to the conductor region and a second hydrogen-free region corresponding to the semiconductor region.

### Claim 4

A method for manufacturing a TFT, comprising:
forming a hydrogen-containing buffer layer on a substrate;
forming an oxide semiconductor layer on the buffer layer;
allowing hydrogen in the buffer layer to enter into a portion of the oxide semiconductor layer such that the oxide semiconductor layer is plasmon activated, the plasmon generated oxide semiconductor layer being formed as a conductor region, and the plasmon non-generated oxide semiconductor layer being formed as a semiconductor region;
forming a source or drain on the conductor region, the source or drain being electrically connected to the conductor region; and
forming a gate structure on the semiconductor region.

### Claim 5 (depends on 4)

The method according to claim 4, wherein before the oxide semiconductor layer is formed, the method further comprises:
forming a patterned blocking layer on the buffer layer, wherein the blocking layer blocks hydrogen in the buffer layer from entering into the oxide semiconductor layer.

### Claim 6 (depends on 4)

The method according to claim 4, wherein
the step of forming a hydrogen-containing buffer layer on a substrate comprises:
forming a hydrogen-free buffer layer on the substrate;
forming a patterned photoresist on the hydrogen-free buffer layer;
performing a hydrogen injection treatment on the buffer layer which is not covered by the photoresist to obtain a first hydrogen-containing region, the buffer layer covered by the photoresist being formed as a second hydrogen-free region; and
removing the photoresist.

### Claim 7 (depends on 4)

The method according to claim 4, wherein,
the step of forming a hydrogen-containing buffer layer on a substrate comprises:
forming a hydrogen-free material layer on the substrate;
forming an opening in the hydrogen-free material layer to expose the substrate;
forming a hydrogen-containing material layer in the opening;
planarizing in such a manner that surfaces away from the substrate of the hydrogen-free material layer and the hydrogen-containing material layer are aligned with each other, wherein the hydrogen-containing material layer is formed as a first region, and the hydrogen-free material layer is formed into a second region.

### Claim 8 (depends on 4)

The method according to claim 4, wherein a content of hydrogen in the buffer layer is selected based on a thickness of the oxide semiconductor layer.

### Claim 9 (depends on 4)

The method according to claim 4, wherein the step of allowing hydrogen in the buffer layer to enter into a portion of the oxide semiconductor layer such that the oxide semiconductor layer is plasmon activated comprises thermal treating the buffer layer.

### Claim 10 (depends on 1)

An array substrate, comprising the thin film transistor according to claim 1.

### Claim 11 (depends on 10)

A display panel, comprising the array substrate according to claim 10.

### Claim 12 (depends on 11)

A display device, comprising the display panel according to claim 11.

### Claim 13 (depends on 1)

The TFT according to claim 1, wherein the hydrogen-containing buffer layer comprises a first region corresponding to the conductor region and a second region corresponding to the semiconductor region, and wherein the first region and the second region comprises SiNx and SiOx respectively.