# US 2019/0172949 A1 · Fabricating method of fin structure with tensile stress and complementary finfet structure

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- Number: US 2019/0172949 A1
- Document ID: US20190172949A1
- Status: Published application
- Kind: A1
- Application number: 16/252,521
- Filed: 2019-01-18
- Published: 2019-06-06
- Earliest claimed: 2017-07-18
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Kai-Lin Lee; Zhi-Cheng Lee; Wei-Jen Chen; Ting-Hsuan Kang; Ren-Yu He; Hung-Wen Huang; Chi-Hsiao Chen; Hao-Hsiang Yang; An-Shih Shih; Chuang-Han Hsieh
- Web page: https://patentgrep.com/patent/US20190172949A1

## CPC

- H10D 30/795: {being in lateral device isolation regions, e.g. STI}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/853: {comprising FinFETs}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.

## Claims

### Claim 1

A fabricating method of a fin structure with tensile stress, comprising:
providing a substrate comprising an N-type transistor region and a P-type transistor region;
forming two first trenches and two second trenches within the substrate, wherein the first trenches define a fin structure, and the second trenches segment the first trenches;
performing a flowable chemical vapor deposition process to form a silicon oxide layer in the first trenches and the second trenches;
planarizing the silicon oxide layer, wherein after planarizing the silicon oxide layer, a top surface of the silicon oxide layer is not lower than a top surface of the fin structure;
forming a patterned mask layer only within the N-type transistor region, wherein the patterned mask layer only overlaps the silicon oxide layer within the second trenches;
removing part of the silicon oxide layer by taking the patterned mask layer as a mask to make both the top surface of the silicon oxide layer in the first trenches within the N-type transistor region and the top surface of the silicon oxide layer within the P-type transistor region lower than the top surface of the fin structure; and
removing the patterned mask layer.

### Claim 2 (depends on 1)

The fabricating method of a fin structure with tensile stress of claim 1, wherein:
after planarizing the silicon oxide layer and before forming the patterned mask layer, the top surface of the silicon oxide layer is higher than the top surface of the fin structure; and
after removing the patterned mask layer, the top surface of the silicon oxide layer within the second trenches within the N-type transistor region is higher than the top surface of the fin structure.

### Claim 3 (depends on 1)

The fabricating method of a fin structure with tensile stress of claim 1, wherein:
after planarizing the silicon oxide layer and before forming the patterned mask layer, the top surface the silicon oxide layer is aligned with the top surface of the fin structure; and
after removing the patterned mask layer, the top surface of the silicon oxide layer within the second trenches within the N-type transistor region is aligned with the top surface of the fin structure.

### Claim 4 (depends on 1)

The fabricating method of a fin structure with tensile stress of claim 1, wherein the patterned mask layer is not formed within the P-type transistor region.

### Claim 5 (depends on 4)

The fabricating method of a fin structure with tensile stress of claim 4, wherein the top surface of the silicon oxide layer in the second trenches within the P-type transistor region is aligned with the silicon oxide layer in the first trenches within the P-type transistor region.