# US 2019/0172948 A1 · High Voltage Switching Device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0172948 A1 - Document ID: US20190172948A1 - Status: Published application - Kind: A1 - Application number: 15/832,626 - Filed: 2017-12-05 - Published: 2019-06-06 - Earliest claimed: 2017-12-05 - Assignees: pSemi Corporation - Applicants: pSemi Corporation - Inventors: Abhijeet Paul; Simon Edward Willard; Alain Duvallet - Web page: https://patentgrep.com/patent/US20190172948A1 ## CPC - H10D 30/637: {Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs} - H10D 30/023: {having multiple independently-addressable gate electrodes influencing the same channel (manufacture or treatment of dual gate TFTs H10D30/031)} - H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)} - H10D 30/657: {having substrates comprising insulating layers, e.g. SOI-LDMOS transistors} - H10D 30/6704: {having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device} - H10D 30/6717: {the source and the drain regions being asymmetrical} - H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current} - H10D 62/378: {Contact regions to the substrate regions} - H10D 64/112: {comprising multiple field plate segments} - H10D 86/01: Manufacture or treatment - H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)} - H10W 20/021: {of interconnections within wafers or substrates} - H10D 62/126: {Top-view geometrical layouts of the regions or the junctions} - H10D 62/157: {Impurity concentrations or distributions} - H10D 64/519: {characterised by their top-view geometrical layouts} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A high-voltage switching device that can be fabricated in a standard low-voltage process, such as CMOS, and more specifically SOI CMOS. Embodiments include integrated circuits that combine, in a unitary structure, a FET device and an integrated, co-fabricated modulated resistance region (MRR) controlled by one or more Voltage-Drop Modulation Gates (VDMGs). The VDMGs are generally biased independently of the gate of the FET device, and in such a way as to protect each VDMG from excessive and potentially destructive voltages. In a first embodiment, an integrated circuit high voltage switching device includes a transistor structure including a source, a gate, and an internal drain; an MRR connected to the internal drain of the transistor structure; at least one VDMG that controls the resistance of the MRR; and a drain electrically connected to the MRR. Each VDMG at least partially depletes the MRR upon application of a bias voltage. ## Claims ### Claim 1 (canceled) ### Claim 2 (canceled) ### Claim 3 At least one integrated circuit high voltage switching device, including: (a) a transistor structure including a source, a gate, an internal drain, and a channel between the source and internal drain; (b) a modulated resistance region co-fabricated with the transistor structure and electrically connected to the internal drain of the transistor structure; (c) at least one voltage-drop modulation gate, fabricated with respect to the modulated resistance region so as to control the resistance of the modulated resistance region; and (d) a drain electrically connected to the modulated resistance region and configured to be coupled to a voltage source; wherein (1) when a first bias voltage is applied to the at least one voltage-drop modulation gate and the FET transistor structure is switched ON, the modulated resistance region provides a low-resistance conduction path current between the source and the drain, and (2) when a second bias voltage is applied to the at least one voltage-drop modulation gate, the modulated resistance region is sufficiently depleted so as to provide a high-resistance to conduction of current between the drain and the internal drain and thereby drop an applied voltage on the drain to less than the breakdown voltage BVDSS of the FET transistor structure. ### Claim 4 (depends on 3) The invention of claim 3, further including a plurality of voltage-drop modulation gates series-connected between the internal drain and the drain. ### Claim 5 (depends on 3) The invention of claim 3, wherein the source, internal drain, and drain of at least one integrated circuit high voltage switching device comprise semiconductor regions of a first polarity, and the channel comprises a semiconductor region of a second polarity. ### Claim 6 (depends on 5) The invention of claim 5, wherein the first polarity is N-type material and the second polarity is P-type material. ### Claim 7 (depends on 5) The invention of claim 5, wherein the first polarity is P-type material and the second polarity is N-type material. ### Claim 8 (depends on 3) The invention of claim 3, wherein the source, internal drain, and drain of at least one integrated circuit high voltage switching device comprise semiconductor regions of a first polarity, and the channel comprises a semiconductor region of a second polarity, and wherein the source, internal drain, and drain of at least another integrated circuit high voltage switching device comprise semiconductor regions of the second polarity, and the channel comprises a semiconductor region of the first polarity. ### Claim 9 (depends on 8) The invention of claim 8, wherein the first polarity is N-type material and the second polarity is P-type material. ### Claim 10 At least one integrated circuit high voltage switching device, including: (a) a transistor structure including a source, a gate, an internal drain, and a channel between the source and internal drain; (b) a modulated resistance region co-fabricated with the transistor structure and electrically connected to the internal drain of the transistor structure; (c) at least one voltage-drop modulation gate, fabricated with respect to the modulated resistance region so as to control the resistance of the modulated resistance region; and (d) a drain electrically connected to the modulated resistance region and configured to be coupled to a voltage source; wherein the modulated resistance region comprises a semiconductor region of the first polarity, doped up to about 5 orders of magnitude less than the source and drain. ### Claim 11 (depends on 10) The invention of claim 10, wherein the at least one voltage-drop modulation gate controls the resistance of the modulated resistance region by at least partially depleting at least a portion of the modulated resistance region upon application of a bias voltage to the at least one voltage-drop modulation gate. ### Claim 12 (depends on 10) The invention of claim 10, wherein the at least one voltage-drop modulation gate controls the resistance of the modulated resistance region by fully depleting at least a portion of the modulated resistance region upon application of a bias voltage to the at least one voltage-drop modulation gate. ### Claim 13 (depends on 3) The invention of claim 3, wherein the integrated circuit is fabricated on a silicon-on-sapphire substrate. ### Claim 14 (depends on 3) The invention of claim 3, wherein the integrated circuit is fabricated on a silicon-on-insulator substrate. ### Claim 15 At least one integrated circuit high voltage switching device fabricated on a silicon-on-insulator substrate, including: (a) a transistor structure including a source, a gate, an internal drain, and a channel between the source and internal drain; (b) a modulated resistance region co-fabricated with the transistor structure and electrically connected to the internal drain of the transistor structure; (c) at least one voltage-drop modulation gate, fabricated with respect to the modulated resistance region so as to control the resistance of the modulated resistance region; (d) a drain electrically connected to the modulated resistance region and configured to be coupled to a voltage source; (e) a deep well region proximate to at least a portion of the modulated resistance region; and (f) at least one substrate contact in electrical contact with the deep well region for applying a bias voltage to the deep well region. ### Claim 16 (depends on 15) The invention of claim 15, wherein the deep well region is the same polarity as the modulated resistance region. ### Claim 17 (depends on 15) The invention of claim 15, wherein the at least one voltage-drop modulation gate controls the resistance of the modulated resistance region by at least partially depleting at least a portion of the modulated resistance region upon application of a first bias voltage to the at least one voltage-drop modulation gate, and wherein the deep well region further depletes at least a portion of the modulated resistance region upon application of a second bias voltage to the at least one substrate contact. ### Claim 18 (depends on 3) The invention of claim 3, wherein the breakdown voltage per voltage-drop modulation gate is at least about 4V. ### Claim 19 (depends on 3) The invention of claim 3, wherein the breakdown voltage per voltage-drop modulation gate is greater than the breakdown voltage of the transistor structure. ### Claim 20 (depends on 3) The invention of claim 3, wherein the integrated circuit high voltage switching device is made using a CMOS process. ### Claim 21 (depends on 3) The invention of claim 3, wherein surface regions of the modulated resistance region adjacent the at least one voltage-drop modulation gate are doped with a material having a first polarity and at a higher doping concentration than the modulated resistance region under the at least one voltage-drop modulation gate. ### Claim 22 (depends on 3) The invention of claim 3, wherein a silicide layer is formed on surface regions of the modulated resistance region adjacent the least one voltage-drop modulation gate. ### Claim at position 23 23-45. (canceled) ### Claim 46 (depends on 3) The invention of claim 3, wherein when the second bias voltage is sufficiently negative with respect to a threshold voltage for the modulated resistance region, the modulated resistance region is fully depleted and pinches off all current through the modulated resistance region. ### Claim 47 At least one integrated circuit high voltage switching device, including: (a) a transistor structure including a source, a gate, an internal drain, and a channel between the source and internal drain; (b) a modulated resistance region co-fabricated with the transistor structure and electrically connected to the internal drain of the transistor structure; (c) at least one voltage-drop modulation gate, fabricated with respect to the modulated resistance region so as to control the resistance of the modulated resistance region; and (d) a drain electrically connected to the modulated resistance region and configured to be coupled to a voltage source; wherein the modulated resistance region comprises a semiconductor region of the first polarity, doped to at least about 2 orders of magnitude less than the source and drain. ### Claim 48 (depends on 47) The invention of claim 47, wherein the modulated resistance region comprises a semiconductor region of the first polarity, doped to at least about 3 orders of magnitude less than the source and drain.