# US 2019/0172947 A1 · Thin film transistors with epitaxial source/drain and drain field relief

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- Number: US 2019/0172947 A1
- Document ID: US20190172947A1
- Status: Published application
- Kind: A1
- Application number: 16/217,701
- Filed: 2018-12-12
- Published: 2019-06-06
- Earliest claimed: 2017-12-06
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Bahman Hekmatshoartabari; Ghavam G. Shahidi; Marinus P.J. Hopstaken
- Web page: https://patentgrep.com/patent/US20190172947A1

## CPC

- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- C30B 23/025: {characterised by the substrate}
- G02F 1/136277: {formed on a semiconductor substrate, e.g. of silicon}
- H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 30/6715: {characterised by the doping profiles, e.g. having lightly-doped source or drain extensions}
- H10D 30/6731: {Top-gate only TFTs}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/2921: {being crystalline insulating materials}
- H10P 14/2922: {being non-crystalline insulating materials, e.g. glass or polymers}
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3442: {N-type}
- H10P 14/3444: {P-type}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- C30B: SINGLE-CRYSTAL GROWTH (by using ultra-high pressure, e.g. for the formation of diamonds, B01J3/06); UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL (zone-refining of metals or alloys C22B); PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE (casting of metals, casting of other substances by the same processes or devices B22D; working of plastics B29; modifying the physical structure of metals or alloys C21D, C22F); SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE (for producing semiconductor devices or parts thereof H10); APPARATUS THEREFOR
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for manufacturing a semiconductor device includes forming a semiconductor layer on an insulating layer, epitaxially growing a first layer on the semiconductor layer, wherein the first layer has a first doping concentration, epitaxially growing a second layer on the semiconductor layer, wherein the second layer has a second doping concentration higher than the first doping concentration, forming a gate dielectric over an active region of the semiconductor layer, forming a gate electrode on the gate dielectric, and forming a plurality of source/drain contacts to the second layer, wherein the first and second layers comprise crystalline hydrogenated silicon (c-Si:H).

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor layer on an insulating layer;
a first doped layer on the semiconductor layer, wherein the first doped layer has a first doping concentration;
a second doped layer on the semiconductor layer, wherein the second doped layer has a second doping concentration higher than the first doping concentration;
a gate dielectric over an active region of the semiconductor layer;
a gate electrode on the gate dielectric; and
one or more source/drain contacts to the second doped layer;
wherein the first doped layer comprises a lightly doped drain (LDD) region and the second doped layer comprises a source/drain region; and
wherein the first and second doped layers comprise crystalline hydrogenated silicon (c-Si:H).

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the crystalline hydrogenated silicon (c-Si:H) comprises about 5 atomic percent hydrogen to about 40 atomic percent hydrogen.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the semiconductor layer comprises poly-silicon.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the first doping concentration is in the range of about 5×1017 cm−3 to about 1×1019 cm−3.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, wherein the second doping concentration is in the range of about 1×1019 cm−3 to about 5×1020 cm−3.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the second doped layer is disposed on the first doped layer.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein the gate dielectric covers at least a portion of the first doped layer.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, wherein the gate dielectric covers an entire portion of the first doped layer.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein at least one of the first and second doped layers are disposed on a top surface and a side surface of the semiconductor layer.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, wherein a portion of the semiconductor layer is recessed.

### Claim 11 (depends on 10)

The semiconductor device according to claim 10, wherein at least one of the first and second doped layers are disposed on the recessed portion of the semiconductor layer.

### Claim 12 (depends on 1)

The semiconductor device according to claim 1, further comprising a passivation layer disposed on the second doped layer, wherein the one or more source/drain contacts are disposed through the passivation layer.

### Claim 13

A semiconductor device, comprising:
a semiconductor layer on an insulating layer;
a first doped layer on the semiconductor layer, wherein the first doped layer has a first doping concentration;
a second doped layer on the semiconductor layer, wherein the second doped layer has a second doping concentration higher than the first doping concentration;
a gate dielectric over an active region of the semiconductor layer; and
a gate electrode on the gate dielectric;
wherein the second doped layer comprises a source/drain region; and
wherein the first and second doped layers comprise crystalline hydrogenated silicon (c-Si:H).

### Claim 14 (depends on 13)

The semiconductor device according to claim 13, wherein the crystalline hydrogenated silicon (c-Si:H) comprises about 5 atomic percent hydrogen to about 40 atomic percent hydrogen.

### Claim 15 (depends on 13)

The semiconductor device according to claim 13, wherein the first doping concentration is in the range of about 5×1017 cm−3 to about 1×1019 cm−3.

### Claim 16 (depends on 15)

The semiconductor device according to claim 15, wherein the second doping concentration is in the range of about 1×1019 cm−3 to about 5×1020 cm−3.

### Claim 17 (depends on 13)

The semiconductor device according to claim 13, wherein the second doped layer is disposed on the first doped layer.

### Claim 18 (depends on 13)

The semiconductor device according to claim 13, wherein the gate dielectric covers at least a portion of the first doped layer.

### Claim 19 (depends on 13)

The semiconductor device according to claim 13, wherein at least one of the first and second doped layers are disposed on a top surface and a side surface of the semiconductor layer.

### Claim 20

A semiconductor device, comprising:
a semiconductor layer on an insulating layer;
a first doped layer on the semiconductor layer, wherein the first doped layer has a first doping concentration; and
a second doped layer on the semiconductor layer, wherein the second doped layer has a second doping concentration higher than the first doping concentration;
wherein the first doped layer comprises a lightly doped drain (LDD) region and the second doped layer comprises a source/drain region; and
wherein the first and second doped layers comprise crystalline hydrogenated silicon (c-Si:H).