# US 2019/0172945 A1 · Folded channel trench mosfet

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0172945 A1
- Document ID: US20190172945A1
- Status: Published application
- Kind: A1
- Application number: 16/264,540
- Filed: 2019-01-31
- Published: 2019-06-06
- Earliest claimed: 2016-11-30
- Assignees: Alpha and Omega Semiconductor Incorporated
- Applicants: Alpha and Omega Semiconductor Incorporated
- Inventors: Sik Lui
- Web page: https://patentgrep.com/patent/US20190172945A1

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 62/154: {Dispositions}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/2527: {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10P 30/22: using masks
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A trench MOSFET device is fabricated with body source regions that undulate along a channel width direction of the MOSFET device such that the body region and source region have variations in depth along the channel width direction. The undulations increase a channel width of the MOSFET device.

## Claims

### Claim 1

A method for fabricating a trench MOSFET device, comprising:
forming a lightly doped epitaxial layer of a first conductivity type on a heavily doped semiconductor substrate of the first conductivity type;
forming an gate electrode into the lightly doped epitaxial layer;
forming a body region of a second conductivity type opposite to the first conductivity type provided in portions of the lightly doped epitaxial layer, wherein the body region has a first undulation along the channel width direction; and
forming a source region of the first conductivity type provided in top portions of the body region, wherein the source region has a second undulation along the channel width direction above the first undulation.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first conductivity type is an N type and the second conductivity type is a P type.

### Claim 3 (depends on 1)

The method of claim 1, wherein the lightly doped epitaxial layer has a third undulation along a channel width direction of the MOSFET device.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming a lightly doped epitaxial layer of a first conductivity type on a heavily doped semiconductor substrate of the first conductivity type comprises:
forming a first epitaxial layer on the semiconductor substrate;
forming a buried layer using a first mask, wherein the first mask defines the third undulation; and
forming a second epitaxial layer on the buried layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein forming an gate electrode into the lightly doped epitaxial layer comprises:
forming a gate trench into the lightly doped epitaxial layer using a second mask, wherein the second mask defines the gate trench;
lining an inner surface of the gate trench with an insulating material; and
filling the gate trench with a conductive material with an etch back.

### Claim 6 (depends on 1)

The method of claim 1, wherein forming a body region of a second conductivity type opposite to the first conductivity type provided in portions of the lightly doped epitaxial layer comprises:
forming a layer of a first insulating material over the lightly doped epitaxial layer;
forming a layer of a second insulating material over the layer of the first insulating material, wherein the layer of the first insulating material is resistant to an etch process that etches the layer of the second insulating material;
forming a third mask on the lightly doped epitaxial layer, wherein the third mask has an opening to define the first undulation; and
implanting dopants of the second conductivity into the lightly doped epitaxial layer to form the body region, wherein the dopants of the second conductivity are implanted deeper into the lightly doped epitaxial layer under the opening to form the first undulation.

### Claim 7 (depends on 6)

The method of claim 6, wherein the first insulating material is nitride.

### Claim 8 (depends on 6)

The method of claim 6, wherein the second insulating material is oxide.

### Claim 9 (depends on 6)

The method of claim 6, wherein the layer of the first insulating material has a thickness of about 200 Å to 500 Å.

### Claim 10 (depends on 6)

The method of claim 6, wherein the layer of the second insulating material has a thickness of about 500 Å to 1000 Å.

### Claim 11 (depends on 6)

The method of claim 6, wherein an angle of the first undulation follows a slope of the opening.

### Claim 12 (depends on 1)

The method of claim 1, wherein forming a source region of the first conductivity type provided in top portions of the body region comprises:
forming the body region using a third mask, wherein the third mask has an opening to define the first undulation; and
implanting dopants of the first conductivity type into the body region to form the source region, wherein the dopants of the first conductivity are implanted deeper into the body region under the opening to form the second undulation.

### Claim 13 (depends on 1)

The method of claim 1 further comprising:
forming a contact trench using a contact trench mask;
lining an inner surface of the contact trench with a first conductive material;
filling the contact trench with a second conductive material, wherein the second conductive material is different from the first conductive material; and
etching back the second conductive material.
