# US 2019/0172943 A1 · Silicon carbide semiconductor device

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- Number: US 2019/0172943 A1
- Document ID: US20190172943A1
- Status: Published application
- Kind: A1
- Application number: 16/095,532
- Filed: 2017-02-27
- Published: 2019-06-06
- Earliest claimed: 2016-04-22
- Assignees: Sumitomo Electric Industries, Ltd.
- Applicants: Sumitomo Electric Industries, Ltd.
- Inventors: Mitsuhiko Sakai; Toru Hiyoshi; So Tanaka
- Web page: https://patentgrep.com/patent/US20190172943A1

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 8/60: Schottky-barrier diodes
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/81: of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
- H10D 62/8325: {Silicon carbide}
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 64/64: Electrodes comprising a Schottky barrier to a semiconductor
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A silicon carbide substrate includes a first impurity region, a second impurity region in contact with the first impurity region and having p type, a third impurity region on the first impurity region and the second impurity region and having n type, a body region, and a source region. A gate insulating film is in contact with the source region, the body region and the third impurity region at a side surface, and in contact with the third impurity region at a bottom surface. When viewed in a direction perpendicular to a main surface, the second impurity region contains the bottom surface, and an area of the second impurity region is greater than an area of the bottom surface, and is not more than three times the area of the bottom surface. An impurity concentration of the second impurity region exceeds 1×1019 cm−3, and is not more than 1×1021 cm−3.

## Claims

### Claim 1

A silicon carbide semiconductor device comprising:
a silicon carbide substrate having a main surface; and
a gate insulating film on the silicon carbide substrate,
the silicon carbide substrate including
a first impurity region having n type,
a second impurity region in contact with the first impurity region and having p type,
a third impurity region, on the first impurity region and the second impurity region, having an impurity concentration higher than that of the first impurity region, and having n type,
a body region on the third impurity region and having p type, and
a source region, on the body region, separated from the third impurity region by the body region, and having n type, wherein
the main surface is provided with a trench defined by a side surface and a bottom surface continuous with the side surface,
the gate insulating film is in contact with the source region, the body region and the third impurity region at the side surface, and is in contact with the third impurity region at the bottom surface,
when viewed in a direction perpendicular to the main surface, the second impurity region contains the bottom surface, and an area of the second impurity region is greater than an area of the bottom surface, and is not more than three times the area of the bottom surface, and
an impurity concentration of the second impurity region exceeds 1×1019 cm−3, and is not more than 1×1021 cm−3.

### Claim 2 (depends on 1)

The silicon carbide semiconductor device according to claim 1, wherein
when viewed in the direction perpendicular to the main surface, an outer edge of the second impurity region is spaced from an outer edge of the bottom surface around an entire periphery of the bottom surface.

### Claim 3 (depends on 1)

The silicon carbide semiconductor device according to claim 1, wherein
a thickness of the second impurity region in the direction perpendicular to the main surface is not less than 0.7 μm.

### Claim 4 (depends on 1)

The silicon carbide semiconductor device according to claim 1, wherein
in a direction parallel to the main surface, a width of an opening in the trench is greater than a width of the bottom surface and smaller than a width of the second impurity region.

### Claim 5 (depends on 1)

The silicon carbide semiconductor device according to claim 1, wherein
in a direction parallel to the main surface, a width of the second impurity region is greater than a width of the bottom surface and smaller than a width of an opening in the trench.

### Claim 6

A silicon carbide semiconductor device comprising:
a silicon carbide substrate having a main surface; and
a gate insulating film on the silicon carbide substrate,
the silicon carbide substrate including
a first impurity region having n type,
a second impurity region in contact with the first impurity region and having p type,
a third impurity region, on the first impurity region and the second impurity region, having an impurity concentration higher than that of the first impurity region, and having n type,
a body region on the third impurity region and having p type, and
a source region, on the body region, separated from the third impurity region by the body region, and having n type, wherein
the main surface is provided with a trench defined by a side surface and a bottom surface continuous with the side surface,
the gate insulating film is in contact with the source region, the body region and the third impurity region at the side surface, and is in contact with the third impurity region at the bottom surface,
when viewed in a direction perpendicular to the main surface, the second impurity region contains the bottom surface, and an area of the second impurity region is greater than an area of the bottom surface, and is not more than three times the area of the bottom surface,
an impurity concentration of the second impurity region exceeds 1×1019 cm−3, and is not more than 1×1021 cm−3,
when viewed in the direction perpendicular to the main surface, an outer edge of the second impurity region is spaced from an outer edge of the bottom surface around an entire periphery of the bottom surface, and
in a direction parallel to the main surface, a width of an opening in the trench is greater than a width of the bottom surface and smaller than a width of the second impurity region.

### Claim 7

A silicon carbide semiconductor device comprising:
a silicon carbide substrate having a main surface; and
a gate insulating film on the silicon carbide substrate,
the silicon carbide substrate including
a first impurity region having n type,
a second impurity region in contact with the first impurity region and having p type,
a third impurity region, on the first impurity region and the second impurity region, having an impurity concentration higher than that of the first impurity region, and having n type,
a body region on the third impurity region and having p type, and
a source region, on the body region, separated from the third impurity region by the body region, and having n type, wherein
the main surface is provided with a trench defined by a side surface and a bottom surface continuous with the side surface,
the gate insulating film is in contact with the source region, the body region and the third impurity region at the side surface, and is in contact with the third impurity region at the bottom surface,
when viewed in a direction perpendicular to the main surface, the second impurity region contains the bottom surface, and an area of the second impurity region is greater than an area of the bottom surface, and is not more than three times the area of the bottom surface,
an impurity concentration of the second impurity region exceeds 1×1019 cm−3, and is not more than 1×1021 cm−3,
when viewed in the direction perpendicular to the main surface, an outer edge of the second impurity region is spaced from an outer edge of the bottom surface around an entire periphery of the bottom surface, and
in a direction parallel to the main surface, a width of the second impurity region is greater than a width of the bottom surface and smaller than a width of an opening in the trench.