# US 2019/0172940 A1 · Utilizing multilayer gate spacer to reduce erosion of semiconductor fin during spacer patterning

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0172940 A1
- Document ID: US20190172940A1
- Status: Published application
- Kind: A1
- Application number: 16/267,618
- Filed: 2019-02-05
- Published: 2019-06-06
- Earliest claimed: 2017-06-30
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Andrew M. Greene; Hong He; Sivananda K. Kanakasabapathy; Gauri Karve; Eric R. Miller; Pietro Montanini
- Web page: https://patentgrep.com/patent/US20190172940A1

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).

## Claims

### Claim 1

A semiconductor device, comprising:
a gate structure formed over a portion of a vertical semiconductor fin of a FinFET (field effect transistor) device; and
a multilayer gate spacer formed on sidewalls of the gate structure;
wherein the multilayer gate spacer comprises a first dielectric layer and a second dielectric layer; and
wherein the first dielectric layer comprises a material that has an etch selectivity with respect to materials of the vertical semiconductor fin and the second dielectric layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first dielectric layer comprises silicon oxycarbonitride (SiOCN).

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the first dielectric layer has a thickness in a range of about 2 nm to about 5 nm.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the second dielectric layer comprises silicon boron carbon nitride (SiBCN).

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the second dielectric layer has a thickness in a range of about 5 nm to about 20 nm.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising epitaxial semiconductor material formed on source/drain regions of the vertical semiconductor fin adjacent to the gate structure.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the gate structure comprises a metallic gate structure.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the metallic gate structure comprises a high-k metal gate structure.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the high-k metal gate structure comprises:
a high-k gate dielectric layer;
a work function metal layer; and
a metal gate electrode.

### Claim 10

A semiconductor device, comprising:
a gate structure formed over a portion of a vertical semiconductor fin of a FinFET (field effect transistor) device; and
a multilayer gate spacer formed on sidewalls of the gate structure;
wherein the multilayer gate spacer comprises a first dielectric layer and a second dielectric layer;
wherein the first dielectric layer comprises a dielectric material that has an etch selectivity of about 10:1 or more with respect to the vertical semiconductor fin and the second dielectric layer; and
wherein the second dielectric layer has an etch selectivity of about 10:1 or more with respect to the first dielectric layer.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the first and second dielectric materials comprise low-k dielectric materials having a dielectric constant that is less than 3.9.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the first dielectric layer comprises silicon oxycarbonitride (SiOCN).

### Claim 13 (depends on 10)

The semiconductor device of claim 10, wherein the second dielectric layer comprises silicon boron carbon nitride (SiBCN).

### Claim 14 (depends on 10)

The semiconductor device of claim 10, wherein the first dielectric layer has a thickness in a range of about 2 nm to about 5 nm, and wherein the second dielectric layer has a thickness in a range of about 5 nm to about 20 nm.

### Claim 15 (depends on 10)

The semiconductor device of claim 10, further comprising epitaxial semiconductor material formed on source/drain regions of the vertical semiconductor fin adjacent to the gate structure.

### Claim 16 (depends on 10)

The semiconductor device of claim 10, wherein the gate structure comprises a high-k metal gate structure, wherein the high-k metal gate structure comprises:
a high-k gate dielectric layer;
a work function metal layer; and
a metal gate electrode.

### Claim 17

A semiconductor device, comprising:
a gate structure formed over a portion of a vertical semiconductor fin of a FinFET (field effect transistor) device; and
a multilayer gate spacer formed on sidewalls of the gate structure;
wherein the multilayer gate spacer comprises a first dielectric layer and a second dielectric layer;
wherein the first dielectric layer comprises silicon oxycarbonitride (SiOCN), and wherein the second dielectric layer comprises silicon boron carbon nitride (SiBCN);
wherein the first dielectric layer has an etch selectivity with respect to materials of the vertical semiconductor fin and the second dielectric layer.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the first dielectric layer has a thickness in a range of about 2 nm to about 5 nm, and wherein the second dielectric layer has a thickness in a range of about 5 nm to about 20 nm.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, further comprising epitaxial semiconductor material formed on source/drain regions of the vertical semiconductor fin adjacent to the gate structure.

### Claim 20 (depends on 17)

The semiconductor device of claim 17, wherein the gate structure comprises a high-k metal gate structure, wherein the high-k metal gate structure comprises:
a high-k gate dielectric layer;
a work function metal layer; and
a metallic gate electrode.