# US 2019/0172939 A1 · Semiconductor device and manufacturing method thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0172939 A1
- Document ID: US20190172939A1
- Status: Published application
- Kind: A1
- Application number: 16/207,067
- Filed: 2018-11-30
- Published: 2019-06-06
- Earliest claimed: 2015-11-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: I-Sheng CHEN; Chih Chieh YEH; Cheng-Hsien WU
- Web page: https://patentgrep.com/patent/US20190172939A1

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/853: {comprising FinFETs}
- H10D 30/798: {being provided in or under the channel regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on each of the first channel layers, a gate electrode layer disposed on the gate dielectric. Each of the first channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire passes through the first source/drain region and enters into an anchor region. At the anchor region, the semiconductor wire has no gate electrode layer and no gate dielectric, and is sandwiched by a second semiconductor material.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked in a first direction;
forming an isolation insulating layer over the fin structure;
forming anchor regions by patterning the isolation insulating layer, thereby partially exposing the fin structure, end portions of the fin structure being buried in the anchor regions;
at least partially removing the second semiconductor layers in the partially exposed fin structure;
forming dummy gate structures with sidewall spacers;
partially removing the sidewall spacers from source/drain regions of the fin structure to partially expose the fin structure in the source/drain regions;
forming epitaxial source/drain structures on the partially exposed fin structure in the source/drain regions; and
forming a gate dielectric layer and a gate electrode layer around the exposed first semiconductor layers in a channel region,
wherein, after the gate electrode layer is formed, a bottom of the source/drain regions of the fin structure are covered by the sidewall spacers.

### Claim 2 (depends on 1)

The method of claim 1, wherein after the gate electrode layer is formed, the first semiconductor layers and the second semiconductor layers are alternately stacked at the anchor regions, and no gate electrode layer and no gate dielectric are included in the anchor regions.

### Claim 3 (depends on 2)

The method of claim 2, wherein:
the first semiconductor layers are made of Si, and
the second semiconductor layers are made of SiGe.

### Claim 4 (depends on 2)

The method of claim 2, wherein:
the first semiconductor layers are made of SiGe, and
the second semiconductor layers are made of Si.

### Claim 5 (depends on 2)

The method of claim 2, wherein the epitaxial source/drain structures include at least one of SiP, SiCP and SiC.

### Claim 6 (depends on 2)

The method of claim 2, wherein the epitaxial source/drain structures include SiGe.

### Claim 7 (depends on 1)

The method of claim 1, wherein the second semiconductor layers are only partially removed in the partially exposed fin structure.

### Claim 8 (depends on 7)

The method of claim 7, wherein the epitaxial source/drain structures cover the first semiconductor layers and the second semiconductor layers in the source/drain regions.

### Claim 9

A semiconductor device, comprising:
first channel layers and a second channel layer disposed over a substrate;
a first source/drain region and a second source/drain region disposed over the substrate;
a first source/drain epitaxial layer covering an upper portion of the first source/drain region, and a second source/drain epitaxial layer covering an upper portion of the second source/drain region;
a first gate dielectric layer disposed on each of the first channel layers and a second gate dielectric layer disposed on the second channel layer;
a gate electrode layer disposed on the first gate dielectric layer and the second gate dielectric layer; and
sidewall spacers disposed on opposing side faces of the gate electrode layer, wherein:
each of the first channel layers includes a semiconductor wire made of a first semiconductor material,
the semiconductor wire passes through the first source/drain region and enters into an anchor region, and
a bottom portion of the first source/drain region and a bottom portion of the second source/drain region are covered by an insulating layer made of a same material as the sidewall spacers.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein at the anchor region, the semiconductor wire has no gate electrode layer and no gate dielectric layer, and is sandwiched by a second semiconductor material different from the first semiconductor material.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein:
the first semiconductor material is made of SiGe, and
the second semiconductor material is Si.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein:
the second channel layer includes a stacked structure of the first semiconductor material and the second semiconductor material.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein:
the first semiconductor material is made of Si, and
the second semiconductor material is made of SiGe.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, wherein at the anchor region, the second channel layer has no gate electrode layer and no gate dielectric layer.

### Claim 15

A semiconductor device, comprising:
a fin structure having a channel layer, source/drain regions and anchored regions;
source/drain epitaxial regions covering an upper portion of the source/drain regions;
a gate dielectric layer disposed on the channel layer;
a gate electrode layer disposed on the gate dielectric layer; and
sidewall spacers disposed on opposing side faces of the gate electrode layer, wherein:
the anchored regions are embedded in anchor regions,
the channel layer includes first semiconductor layers and second semiconductor layers alternately stacked in a vertical direction,
widths of the first semiconductor layers in the channel layer are smaller than widths of the second semiconductor layers in the channel layer,
the widths of the first semiconductor layers in the channel layer are smaller than widths of the first semiconductor layers in the anchor region, and
a bottom portion of the source/drain region is covered by an insulating layer made of a same material as the sidewall spacers.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein at the anchor region, the fin structure has no gate electrode layer and no gate dielectric layer.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein:
the first semiconductor layers are made of SiGe, and
the second semiconductor layers are made of Si.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein:
the first semiconductor layers are made of Si, and
the second semiconductor layers are made of SiGe.

### Claim 19 (depends on 16)

The semiconductor device of claim 16, wherein the source/drain epitaxial regions include at least one of SiP, SiCP and SiC.

### Claim 20 (depends on 16)

The semiconductor device of claim 16, wherein the source/drain epitaxial regions include SiGe.