# US 2019/0172933 A1 · Semiconductor device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0172933 A1
- Document ID: US20190172933A1
- Status: Published application
- Kind: A1
- Application number: 16/207,084
- Filed: 2018-11-30
- Published: 2019-06-06
- Earliest claimed: 2017-12-01
- Assignees: Murata Manufacturing Co., Ltd.
- Applicants: Murata Manufacturing Co., Ltd.
- Inventors: Isao OBU; Yasunari UMEMOTO; Masahiro SHIBATA; Shigeki KOYA; Masao KONDO; Takayuki TSUTSUI
- Web page: https://patentgrep.com/patent/US20190172933A1

## CPC

- H10D 10/821: {Vertical heterojunction BJTs}
- H10D 10/021: {of heterojunction BJTs [HBT]}
- H10D 62/136: {of heterojunction BJTs (vertical heterojunction BJTs having one or more non-monocrystalline Group IV elements H10D10/861)}
- H10D 62/137: {Collector regions of BJTs}
- H10D 62/138: {Pedestal collectors}
- H10D 62/177: {Base regions of bipolar transistors, e.g. BJTs or IGBTs}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 64/0116: {to Group III-V semiconductors}
- H10D 64/281: {Base electrodes for bipolar transistors}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/3414: {being group IIIA-VIA materials}
- H10P 50/646: {of Group III-V materials}
- H10P 50/648: {Anisotropic liquid etching}
- H10P 50/691: {for Group IV materials or Group III-V materials}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A bipolar transistor including a first collector layer, a second collector layer, a base layer, and an emitter layer is disposed on a substrate. Etching characteristics of the second collector layer are different from etching characteristics of the first collector layer and the base layer. In plan view, an edge of an interface between the first collector layer and the second collector layer is disposed inside an edge of a lower surface of the base layer, and an edge of an upper surface of the second collector layer coincides with the edge of the lower surface of the base layer or is disposed inside the edge of the lower surface of the base layer.

## Claims

### Claim 1

A semiconductor device comprising:
a bipolar transistor including a first collector layer, a second collector layer, a base layer, and an emitter layer that are stacked on a substrate,
wherein
a composition of the first collector layer and a composition of the second collector layer are different from each other, and
in plan view, an edge of an interface between the first collector layer and the second collector layer is disposed inside an edge of a lower surface of the base layer, and an edge of an upper surface of the second collector layer coincides with the edge of the lower surface of the base layer or is disposed inside the edge of the lower surface of the base layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the second collector layer has a composition containing phosphorus.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein
in plan view, an edge of an upper surface of the first collector layer, the edge of the upper surface of the second collector layer, and an edge of a lower surface of the second collector layer are disposed inside the edge of the lower surface of the base layer, and
the edge of the lower surface of the second collector layer is disposed inside the edge of the upper surface of the first collector layer.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein in plan view, an edge of an upper surface of the base layer is disposed inside an edge of a lower surface of the emitter layer.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a sub-collector layer disposed between the substrate and the first collector layer and functioning as a current path through which a collector current flows into the first collector layer; and
an etching stopper layer disposed between the sub-collector layer and the first collector layer and made of a semiconductor having the same etching characteristics as the second collector layer,
wherein, in plan view, an edge of an upper surface of the etching stopper layer is disposed inside an edge of a lower surface of the first collector layer.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein
the base layer contains one compound semiconductor selected from the group consisting of GaAs, AlGaAs, InGaAs, GaAsSb, GaAsBi, and GaInNAs as a main component, and
the emitter layer contains InGaP as a main component.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, wherein
the first collector layer and the sub-collector layer contain GaAs as a main component, and
the second collector layer and the etching stopper layer contain InGaP as a main component.

### Claim 8 (depends on 6)

The semiconductor device according to claim 6, wherein
the first collector layer and the sub-collector layer contain GaAs as a main component,
the second collector layer contains InGaPN as a main component, and
the etching stopper layer contains InGaP as a main component.

### Claim 9 (depends on 6)

The semiconductor device according to claim 6, wherein
the first collector layer and the sub-collector layer contain GaAs as a main component, and
the second collector layer and the etching stopper layer contain InGaPN as a main component.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a bump disposed at a position higher than the emitter layer as viewed from the substrate, and connected to the emitter layer in terms of a direct current.

### Claim 11 (depends on 5)

The semiconductor device according to claim 5, further comprising:
a third collector layer disposed between the sub-collector layer and the etching stopper layer and having the same etching characteristics as the first collector layer,
wherein, in plan view, an edge of an upper surface of the third collector layer is disposed outside the edge of the lower surface of the first collector layer.

### Claim 12 (depends on 11)

The semiconductor device according to claim 11, wherein
the base layer contains one compound semiconductor selected from the group consisting of GaAs, AlGaAs, InGaAs, GaAsSb, GaAsBi, and GaInNAs as a main component,
the emitter layer contains InGaP as a main component,
the first collector layer, the third collector layer, and the sub-collector layer contain GaAs as a main component, and
the second collector layer and the etching stopper layer contain InGaP as a main component.

### Claim 13 (depends on 11)

The semiconductor device according to claim 11, wherein
the base layer contains one compound semiconductor selected from the group consisting of GaAs, AlGaAs, InGaAs, GaAsSb, GaAsBi, and GaInNAs as a main component,
the emitter layer contains InGaP as a main component,
the first collector layer, the third collector layer, and the sub-collector layer contain GaAs as a main component,
the second collector layer contains InGaPN as a main component, and
the etching stopper layer contains InGaP as a main component.

### Claim 14 (depends on 11)

The semiconductor device according to claim 11, wherein
the base layer contains one compound semiconductor selected from the group consisting of GaAs, AlGaAs, InGaAs, GaAsSb, GaAsBi, and GaInNAs as a main component,
the emitter layer contains InGaP as a main component,
the first collector layer, the third collector layer, and the sub-collector layer contain GaAs as a main component, and
the second collector layer and the etching stopper layer contain InGaPN as a main component.

### Claim 15 (depends on 11)

The semiconductor device according to claim 11, further comprising:
a bump disposed at a position higher than the emitter layer as viewed from the substrate and connected to the emitter layer in terms of a direct current.

### Claim 16 (depends on 2)

The semiconductor device according to claim 2, wherein
in plan view, an edge of an upper surface of the first collector layer, the edge of the upper surface of the second collector layer, and an edge of a lower surface of the second collector layer are disposed inside the edge of the lower surface of the base layer, and
the edge of the lower surface of the second collector layer is disposed inside the edge of the upper surface of the first collector layer.

### Claim 17 (depends on 2)

The semiconductor device according to claim 2, wherein in plan view, an edge of an upper surface of the base layer is disposed inside an edge of a lower surface of the emitter layer.

### Claim 18 (depends on 2)

The semiconductor device according to claim 2, further comprising:
a sub-collector layer disposed between the substrate and the first collector layer and functioning as a current path through which a collector current flows into the first collector layer; and
an etching stopper layer disposed between the sub-collector layer and the first collector layer and made of a semiconductor having the same etching characteristics as the second collector layer,
wherein, in plan view, an edge of an upper surface of the etching stopper layer is disposed inside an edge of a lower surface of the first collector layer.

### Claim 19 (depends on 2)

The semiconductor device according to claim 2, further comprising:
a bump disposed at a position higher than the emitter layer as viewed from the substrate, and connected to the emitter layer in terms of a direct current.

### Claim 20 (depends on 12)

The semiconductor device according to claim 12, further comprising:
a bump disposed at a position higher than the emitter layer as viewed from the substrate and connected to the emitter layer in terms of a direct current.