# US 2019/0172932 A1 · Manufacturing method of thin film transistor, thin film transistor and display substrate

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- Number: US 2019/0172932 A1
- Document ID: US20190172932A1
- Status: Published application
- Kind: A1
- Application number: 16/322,272
- Filed: 2018-02-01
- Published: 2019-06-06
- Earliest claimed: 2017-06-02
- Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd.
- Applicants: Hefei Xinsheng Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd.
- Inventors: Haijiao QIAN; Binbin CAO; Chengshao YANG; Yinhu HUANG
- Web page: https://patentgrep.com/patent/US20190172932A1

## CPC

- H10D 30/0316: {of lateral bottom-gate TFTs comprising only a single gate}
- H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6731: {Top-gate only TFTs}
- H10D 30/6732: {Bottom-gate only TFTs}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 30/6746: {Amorphous silicon}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10P 50/266: {by vapour etching only}
- H10P 50/283: {by chemical means}
- H10P 50/691: {for Group IV materials or Group III-V materials}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 50/73: {using masks for insulating materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a manufacturing method of thin film transistor, a thin film transistor and a display substrate. The manufacturing method comprises sequentially forming a polysilicon pattern layer and a protective pattern layer on a substrate; etching the protective pattern layer with a first etching gas, so as to obtain a protective pattern; simultaneously etching the protective pattern and the polysilicon pattern layer with a second etching gas by using the protective pattern as a mask, so as to obtain a polysilicon pattern and a residual protective pattern, the protective pattern being etched with the second etching gas at a rate no less than that for etching the polysilicon pattern layer; and forming an amorphous silicon pattern, which is in contact with etched sides of the polysilicon pattern, exposes a part of the residual protective pattern, and forms an active layer together with the polysilicon pattern.

## Claims

### Claim 1

A manufacturing method of thin film transistor, comprising steps of forming an active layer, which comprise:
forming a polysilicon pattern layer and a protective pattern layer on a substrate sequentially;
etching the protective pattern layer with a first etching gas, so as to obtain a protective pattern formed from the protective pattern layer;
simultaneously etching the protective pattern and the polysilicon pattern layer with a second etching gas by using the protective pattern as a mask, so as to obtain a polysilicon pattern formed from the polysilicon pattern layer and a residual protective pattern formed from the protective pattern, wherein the protective pattern is etched with the second etching gas at a rate no less than a rate at which the polysilicon pattern layer is etched with the second etching gas; and
forming an amorphous silicon pattern, which is in contact with etched sides of the polysilicon pattern, exposes a part of the residual protective pattern, and forms an active layer together with the polysilicon pattern.

### Claim 2 (depends on 1)

The manufacturing method of claim 1, wherein, materials for forming the polysilicon pattern layer comprise p-Si, and materials for forming the protective pattern layer comprise SiO2.

### Claim 3 (depends on 2)

The manufacturing method of claim 2, wherein,
the step of etching the protective pattern layer with a first etching gas comprises:
etching the protective pattern layer with the first etching gas composed of O2 and CF4 in a volume ratio of 40:200.

### Claim 4 (depends on 3)

The manufacturing method of claim 3, wherein,
the protective pattern layer has a thickness of about 1000 Å, a period of etching the protective pattern layer with the first etching gas is in a range of 120s to 130s, and an atmospheric pressure of etching environment is in a range of 55 mTorr to 65 mTorr.

### Claim 5 (depends on 2)

The manufacturing method of claim 2, wherein,
the step of simultaneously etching the protective pattern and the polysilicon pattern layer with a second etching gas comprises:
simultaneously etching the protective pattern and the polysilicon pattern layer with the second etching gas composed of O2 and CF4 in a volume ratio of 100:200.

### Claim 6 (depends on 5)

The manufacturing method of claim 5, wherein,
the polysilicon pattern layer has a thickness of about 500 Å, a period of simultaneously etching the protective pattern and the polysilicon pattern layer with the second etching gas is in a range of 35s to 45s, and an atmospheric pressure of etching environment is in a range of 75 mTorr to 85 mTorr.

### Claim 7 (depends on 1)

The manufacturing method of claim 1, further comprising:
after the amorphous silicon pattern is formed, performing ion implantation to a surface of the amorphous silicon pattern away from the substrate, so as to form an ohmic contact layer by an ion implanted part of the amorphous silicon pattern.

### Claim 8

A thin film transistor, comprising an active layer; wherein the active layer comprises:
a polysilicon pattern which has a first surface, a second surface and etched sides, the first surface and the second surface are opposite surfaces of the polysilicon pattern, and the etched sides are located between the first and second surfaces; and an area of the first surface is smaller than that of the second surface;
a residual protective pattern on the first surface; and
an amorphous silicon pattern which is in contact with the etched sides and a part of the first surface, and exposes a part of the residual protective pattern.

### Claim 9 (depends on 8)

The thin film transistor of claim 8, wherein the amorphous silicon pattern is in contact with the entire etched sides.

### Claim 10 (depends on 8)

The thin film transistor of claim 8, wherein a projection area of the residual protective pattern on the first surface is smaller than the area of the first surface.

### Claim 11 (depends on 8)

The thin film transistor of claim 8, wherein the etched sides are obliquely located between the first surface and the second surface.

### Claim 12 (depends on 8)

The thin film transistor of claim 8, wherein the first surface is an upper surface of the polysilicon pattern; the second surface is a lower surface of the polysilicon pattern; and the etched sides extend upwards from the second surface and towards an inside direction of the polysilicon pattern to the first surface.

### Claim 13 (depends on 12)

The thin film transistor of claim 12, wherein an angle between the etched side and the second surface is in a range of 45 degrees to 55 degrees.

### Claim 14 (depends on 8)

The thin film transistor of claim 8, wherein the etched side has a slope ranging from 45 degrees to 55 degrees.

### Claim 15 (depends on 8)

The thin film transistor of claim 8, wherein the polysilicon pattern and the residual protective pattern form an ascending step structure.

### Claim 16 (depends on 8)

A display substrate, comprising the thin film transistor of claim 8.