# US 2019/0172930 A1 · Hybrid active-field gap extended drain mos transistor

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- Number: US 2019/0172930 A1
- Document ID: US20190172930A1
- Status: Published application
- Kind: A1
- Application number: 16/272,025
- Filed: 2019-02-11
- Published: 2019-06-06
- Earliest claimed: 2010-10-26
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Sameer P. PENDHARKAR; John LIN
- Web page: https://patentgrep.com/patent/US20190172930A1

## CPC

- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/158: {Dispositions}
- H10D 64/111: {Field plates}
- H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions.

## Claims

### Claim 1

An integrated circuit, comprising:
an extended drain metal-oxide semiconductor (EDMOS) transistor, including:
a channel region positioned in a semiconductor substrate;
an extended drain positioned in the semiconductor substrate, the extended drain including a drift region having field gap drift regions and active gap regions alternating with the field gap drift regions, the drift region abutting the channel region;
field oxide structures positioned adjacent to the field gap drift regions and opposing the channel region; and
a drain contact diffused region positioned on the extended drain and having a plurality of lateral projections extending toward the channel region, the drain contact diffused region having a higher doping concentration than the extended drain, and the lateral projections interleaving with the field oxide structures;