# US 2019/0172929 A1 · Fabrication Of Vertical Field Effect Transistor Structure With Strained Channels

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- Number: US 2019/0172929 A1
- Document ID: US20190172929A1
- Status: Published application
- Kind: A1
- Application number: 16/264,757
- Filed: 2019-02-01
- Published: 2019-06-06
- Earliest claimed: 2016-05-11
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Juntao Li
- Web page: https://patentgrep.com/patent/US20190172929A1

## CPC

- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 30/796: {having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates}
- H10D 62/117: {Shapes of semiconductor bodies}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of forming a vertical fin field effect transistor (vertical finFET) with a strained channel, including forming one or more vertical fins on a substrate, forming a sacrificial stressor layer adjacent to the one or more vertical fins, wherein the sacrificial stressor layer imparts a strain in the adjacent vertical fins, forming a fin trench through one or more vertical fins and the sacrificial stressor layer to form a plurality of fin segments and a plurality of sacrificial stressor layer blocks, forming an anchor wall adjacent to and in contact with one or more fin segment endwalls, and removing at least one of the plurality of the sacrificial stressor layer blocks, wherein the anchor wall maintains the strain of the adjacent fin segments after removal of the sacrificial stressor layer blocks adjacent to the fin segment with the adjacent anchor wall.

## Claims

### Claim 1

A vertical fin field effect transistor (finFET), comprising;
one or more vertical fins formed on a substrate, wherein the width of the vertical fins is in the range of about 6 nm to about 20 nm;
a doped region in the substrate located below at least one of the one or more vertical fins;
an anchor wall at each end of the one or more vertical fins, where the anchor wall is in contact with the endwall of at least one of the one or more vertical fins, and where the anchor wall maintains the at least one of the one or more vertical fins in a strained state;
a bottom spacer on the substrate and adjacent the sidewall of at least one of the one or more vertical fins;
a gate structure on at least a portion of the sidewalls of at least one of the one or more vertical fins; and
a top spacer on the gate structure opposite the bottom spacer.

### Claim 2 (depends on 1)

The vertical finFET of claim 1, further comprising a top source/drain on the top surface of at least one of the one or more vertical fins.

### Claim 3 (depends on 2)

The vertical finFET of claim 2, wherein the one or more vertical fins have a height in the range of about 25 nm to about 75 nm.

### Claim 4 (depends on 1)

The vertical finFET of claim 1, wherein the vertical fins have a pitch in the range of about 30 nm to about 200 nm.

### Claim 5 (depends on 1)

The vertical finFET of claim 1, wherein the anchor wall is silicon nitride or silicon oxynitride.

### Claim 6 (depends on 1)

The vertical finFET of claim 1, further comprising an interlayer dielectric formed between the anchor walls, and where the substrate is a single crystal Si substrate and the vertical fins are single crystal silicon.

### Claim 7 (depends on 1)

The vertical finFET of claim 1, wherein the bottom space is silicon nitride (SiN), silicon oxide (SiO), silicon oxynitride (SiON), a multi-layer arrangement of silicon oxide and silicon nitride, or combinations thereof.

### Claim 8 (depends on 1)

The vertical finFET of claim 1, wherein the gate structure includes a gate dielectric layer on at least a portion of the sidewalls of at least one of the one or more vertical fins, a work function layer on the gate dielectric layer, and a gate metal layer on the work function layer.

### Claim 9 (depends on 8)

The vertical finFET of claim 8, wherein the gate dielectric layer is a high-K dielectric, and the work function layer is titanium nitride (TiN), hafnium nitride (HfN), hafnium silicon nitride (HfSiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN), titanium carbide (TiC), tantalum carbide (TaC), hafnium carbide (HfC), or combinations thereof.

### Claim 10 (depends on 8)

The vertical finFET of claim 8, wherein the work function layer has a thickness in the range of about 3 nm to about 11 nm, and the gate dielectric layer has a thickness in the range of about 1.5 nm to about 2.5 nm.

### Claim 11

A vertical fin field effect transistor (finFET), comprising;
one or more vertical fins formed on a substrate, wherein the one or more vertical fins are a semiconductor material and each have a height in the range of about 25 nm to about 75 nm;
an anchor wall at each end of the one or more vertical fins, where the anchor wall is in contact with the endwall of the one or more vertical fins, and where the anchor wall is silicon oxide, silicon nitride, or silicon oxynitride, that maintains the vertical fin in a strained state; and
a bottom spacer on the substrate and adjacent the sidewall of at least one of the one or more vertical fins.

### Claim 12 (depends on 11)

The vertical finFET of claim 11, wherein the bottom spacer is silicon nitride (SiN), silicon oxide (SiO), silicon oxynitride (SiON), a multi-layer arrangement of silicon oxide and silicon nitride, or combinations thereof.

### Claim 13 (depends on 11)

The vertical finFET of claim 11, wherein the one or more vertical fins are single crystal silicon (Si) or single crystal silicon germanium (SiGe).

### Claim 14 (depends on 11)

The vertical finFET of claim 11, further comprising a gate dielectric layer on at least a portion of the sidewalls of at least one of the one or more vertical fins, a work function layer on the gate dielectric layer, and a gate metal layer on the work function layer.

### Claim 15 (depends on 14)

The vertical finFET of claim 14, wherein the gate dielectric layer is hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide (Pb(ScxTa1-x)O3), or lead zinc niobate (e.g., PbZn1/3Nb2/3O3).

### Claim 16 (depends on 14)

The vertical finFET of claim 14, wherein the one or more vertical fins have a width in the range of about 10 nm to about 12 nm.

### Claim 17

A vertical fin field effect transistor (finFET), comprising;
one or more vertical fins formed on a substrate, where the one or more vertical fins have a width in the range of about 8 nm to about 15 nm, and a height in the range of about 25 nm to about 75 nm;
an anchor wall at each end of the one or more vertical fins, where the anchor wall is in contact with the endwall of at least one of the one or more vertical fins, and where the anchor wall maintains the at least one of the one or more vertical fins in a strained state; and
a gate structure on at least a portion of the sidewalls of at least one of the one or more vertical fins.

### Claim 18 (depends on 17)

The vertical finFET of claim 17, wherein the anchor wall has a width in the range of about 30 nm to about 500 nm.

### Claim 19 (depends on 17)

The vertical finFET of claim 17, wherein the one or more vertical fins are single crystal silicon (Si) or single crystal silicon germanium (SiGe).

### Claim 20 (depends on 17)

The vertical finFET of claim 17, further comprising a top source/drain on the top surface of at least one of the one or more vertical fins, and a doped region in the substrate located below at least one of the one or more vertical fins.