# US 2019/0172926 A1 · Gate structure for semiconductor device

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- Number: US 2019/0172926 A1
- Document ID: US20190172926A1
- Status: Published application
- Kind: A1
- Application number: 16/204,849
- Filed: 2018-11-29
- Published: 2019-06-06
- Earliest claimed: 2017-08-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Kuo-Cheng CHING; Chih-Hao WANG; Ching-Wei TSAI; Kuan-Lun CHENG
- Web page: https://patentgrep.com/patent/US20190172926A1

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3456: {Polycrystalline}
- H10P 50/242: {of Group IV materials}
- H10P 50/266: {by vapour etching only}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10P 14/6308: {of Group IV semiconductors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a fin field effect transistors (finFET) on a substrate includes forming a fin structure on the substrate, forming a protective layer on the fin structure, and forming a polysilicon structure on the protective layer. The method further includes modifying the polysilicon structure such that a first horizontal dimension of a first portion of the modified polysilicon structure is smaller than a second horizontal dimension of a second portion of the modified polysilicon structure. The method further includes replacing the modified polysilicon structure with a gate structure having a first horizontal dimension of a first portion of the gate structure that is smaller than a second horizontal dimension of a second portion of the gate structure.

## Claims

### Claim 1

A fin field effect transistor (finFET), comprising:
a substrate;
a fin structure on the substrate;
an epitaxial source/drain region on the fin structure;
a gate structure having first and second portions, wherein:
a first horizontal dimension of the first portion is less than a second horizontal dimension of the second portion,
the first portion is above a top surface of the fin structure, and
the second portion is below the top surface of the fin structure; and
a source/drain contact structure, on the epitaxial source/drain region, comprising a barrier layer to prevent an electrical short between the source/drain contact structure and the gate structure.

### Claim 2 (depends on 1)

The finFET of claim 1, wherein the first horizontal dimension of the first portion ranges from about 8 nm to about 12 nm.

### Claim 3 (depends on 1)

The finFET of claim 1, wherein the second horizontal dimension of the second portion ranges from about 10 nm to about 16 nm.

### Claim 4 (depends on 1)

The finFET of claim 1, wherein the gate structure comprises:
an oxide layer on the fin structure;
a dielectric layer on the oxide layer; and
a gate electrode on the dielectric layer.

### Claim 5 (depends on 1)

The finFET of claim 1, wherein the source/drain contact structure comprises:
a metal silicide layer on a top surface of the epitaxial source/drain region;
a conductive region on the metal silicide layer; and
a barrier layer in contact with a sidewall of the conductive region and not in contact with a bottom surface of the conductive region or a top surface of the epitaxial source/drain region.

### Claim 6 (depends on 5)

The finFET of claim 5, further comprising:
an etch stop layer on the gate structure; and
an interlayer dielectric (ILD) layer on the etch stop layer, wherein the barrier layer is on a sidewall of the ILD layer.

### Claim 7 (depends on 1)

The finFET of claim 1, wherein the first horizontal dimension is less than the second horizontal dimension by about 1 nm to about 4 nm.

### Claim 8 (depends on 1)

The finFET of claim 1, wherein a ratio of the first horizontal dimension to the second horizontal dimension is between about 1:1.2 and about 1:1.1.

### Claim 9 (depends on 1)

The finFET of claim 1, wherein the first horizontal dimension is a length of a middle portion of the first portion.

### Claim 10 (depends on 9)

The finFET of claim 9, further comprising third and fourth horizontal dimensions at top and bottom locations of the first portion, wherein the first horizontal dimension is greater than the third or fourth horizontal dimension.

### Claim 11

A fin field effect transistor (finFET), comprising:
a fin structure comprising a top surface, wherein the fin structure extends in a horizontal direction;
a dielectric layer on the fin structure; and
a gate electrode on the dielectric layer, comprising:
a first portion, above the top surface of the fin structure, comprising a first dimension along the horizontal direction; and
a second portion, below the top surface of the fin structure, comprising a second dimension along the horizontal direction, wherein the first dimension is less than the second dimension.

### Claim 12 (depends on 11)

The finFET of claim 11, wherein the first dimension is between about 8 nm and about 12 nm.

### Claim 13 (depends on 11)

The finFET of claim 11, wherein the second dimension is between about 10 nm and about 16 nm.

### Claim 14 (depends on 11)

The finFET of claim 11, wherein the first dimension is a length of a middle portion of the first portion.

### Claim 15 (depends on 14)

The finFET of claim 14, further comprising top and bottom locations of the first portion respectively comprising third and fourth dimensions along the horizontal direction, wherein the first dimension is greater than the third or fourth dimension.

### Claim 16

A fin field effect transistor (finFET), comprising:
a substrate;
a fin structure, on the substrate, comprising a top surface;
a dielectric layer on the fin structure; and
a gate electrode, on the dielectric layer, comprising a first gate length, a second gate length, and a third gate length, wherein:
the first gate length at a top portion of the gate electrode is less than the second gate length at a middle portion of the gate electrode; and
the third gate length at a bottom portion of the gate electrode and below the top surface of the fin structure is greater than the second gate length.

### Claim 17 (depends on 16)

The finFET of claim 16, wherein the second gate length is between about 8 nm and about 12 nm.

### Claim 18 (depends on 16)

The finFET of claim 16, wherein the third gate length is between about 10 nm and about 16 nm.

### Claim 19 (depends on 16)

The finFET of claim 16, wherein the third gate length is greater than the second gate length by about 1 nm to about 4 nm.

### Claim 20 (depends on 16)

The finFET of claim 16, further comprising:
an epitaxial source/drain region on the fin structure; and
a source/drain contact structure, comprising:
a metal silicide layer on a top surface of the epitaxial source/drain region;
a conductive region on the metal silicide layer; and
a barrier layer in contact with a sidewall of the conductive region and not in contact with a bottom surface of the conductive region or a top surface of the epitaxial source/drain region.