# US 2019/0172920 A1 · Junctionless transistor device and method for preparing the same

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- Number: US 2019/0172920 A1
- Document ID: US20190172920A1
- Status: Published application
- Kind: A1
- Application number: 15/862,158
- Filed: 2018-01-04
- Published: 2019-06-06
- Earliest claimed: 2017-12-06
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Tsung-Yu TSAI; Ching-Chia HUANG; Kung-Ming FAN
- Web page: https://patentgrep.com/patent/US20190172920A1

## CPC

- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/615: {comprising a MOS gate electrode and at least one non-MOS gate electrode}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 30/6217: {having non-uniform gate electrodes, e.g. gate conductors having varying doping}
- H10D 30/637: {Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs}
- H10D 30/663: {having both source contacts and drain contacts on the same surface, i.e. up-drain VDMOS}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A functionless transistor device includes a semiconductor substrate, a channel, a first source/drain, a second source/drain, a gate and a gate dielectric layer. The channel includes a first channel extending in a lateral direction, and a second channel extending in a vertical direction. The first source/drain is in contact with the first channel. The second source/drain is in contact with the second channel. The channel, the first source/drain and the second source/drain have the same doping type. The gate is disposed over an upper surface of the first channel and side surfaces of the second channel, and the gate has a second doping type opposite to the first doping type. The gate dielectric layer is disposed between the gate and the channel.

## Claims

### Claim 1

A junctionless transistor device, comprising:
a semiconductor substrate having a surface;
a channel disposed over the semiconductor substrate, wherein the channel comprises a first channel extending in a lateral direction substantially parallel to the surface of the semiconductor substrate, and a second channel extending in a vertical direction substantially perpendicular to the surface of the semiconductor substrate, wherein the first channel and the second channel are in contact at one end, and the channel has a first doping type;
a first source/drain disposed over the semiconductor substrate, and in contact with the first channel, wherein the first source/drain has the first doping type;
a second source/drain disposed over the second channel, and in contact with the second channel, wherein the second source/drain has the first doping type;
a gate disposed over an upper surface of the first channel and side surfaces of the second channel, wherein the gate has a second doping type opposite to the first doping type; and
a gate dielectric layer disposed between the gate and the channel.

### Claim 2 (depends on 1)

The junctionless transistor device of claim 1, wherein a doping concentration of the first source/drain, a doping concentration of the second source/drain and a doping concentration of the channel are substantially the same.

### Claim 3 (depends on 2)

The junctionless transistor device of claim 2, wherein a doping concentration of the gate is higher than a doping concentration of the channel.

### Claim 4 (depends on 1)

The junctionless transistor device of claim 1, wherein the semiconductor substrate includes a doped well under the channel, and the doped well has the second doping type.

### Claim 5 (depends on 4)

The junctionless transistor device of claim 4, wherein a doping concentration of the doped well is lower than a doping concentration of the channel.

### Claim 6 (depends on 1)

The junctionless transistor device of claim 1, further comprising a first electrical contact electrically connected to the first source/drain, and a. second electrical contact electrically connected to the second source/drain.

### Claim 7 (depends on 1)

The junctionless transistor device of claim 1, wherein the gate surrounds a plurality of side surfaces of the second channel.

### Claim 8

A method for preparing a junctionless transistor device, comprising:
providing a semiconductor substrate;
forming a semiconductor doped structure over the semiconductor substrate, wherein the semiconductor doped structure has a first doping type, and the semiconductor doped structure comprises a first doped structure extending in a lateral direction substantially parallel to a surface of the semiconductor substrate, and a second doped structure extending in a vertical direction substantially perpendicular to the surface of the semiconductor substrate; and
forming a gate dielectric layer and a gate over the semiconductor doped structure, wherein the gate has a second doping type opposite to the first doping type.

### Claim 9 (depends on 8)

The method of claim 8, wherein the forming the semiconductor doped structure over the semiconductor substrate comprises:
forming a doped region having the first doping type in the semiconductor substrate; and
patterning the doped region to form the semiconductor doped structure.

### Claim 10 (depends on 8)

The method of claim 8, Wherein the gate dielectric layer and the gate cover an upper surface of the first doped structure and side surfaces of the second doped structure, and expose an upper surface of the second doped structure.

### Claim 11 (depends on 10)

The method of claim 10, wherein the forming the gate dielectric layer and the gate over the semiconductor doped structure comprises:
forming the gate dielectric layer over the semiconductor doped structure;
forming the gate over the gate dielectric layer;
doping the gate; and
partially removing the gate and the gate dielectric layer to expose the upper surface of the second doped structure.

### Claim 12 (depends on 11)

The method of claim 11, Wherein the forming the gate dielectric: layer over the semiconductor doped structure comprises thermally growing a thermal oxide layer over the semiconductor doped structure.

### Claim 13 (depends on 8)

The method of claim 8, wherein a doping concentration of the first doped structure and a doping concentration of the second doped structure are substantially the same.

### Claim 14 (depends on 8)

The method of claim 8, wherein a doping concentration of the gate is higher than a doping concentration of the semiconductor doped structure.

### Claim 15 (depends on 8)

The method of claim 8, wherein an end of the first doped structure is configured as a first source/drain, an end of the second doped structure is configured as a second source/drain, and the first doped structure and the second doped structure are configured as a channel.