# US 2019/0172909 A1 · Transistor device and semiconductor layout structure

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- Number: US 2019/0172909 A1
- Document ID: US20190172909A1
- Status: Published application
- Kind: A1
- Application number: 15/866,888
- Filed: 2018-01-10
- Published: 2019-06-06
- Earliest claimed: 2017-12-01
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: JHEN-YU TSAI; TSENG-FU LU; WEI-MING LIAO
- Web page: https://patentgrep.com/patent/US20190172909A1

## CPC

- H10D 62/152: {Source regions of DMOS transistors}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/117: {Shapes of semiconductor bodies}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 89/10: Integrated device layouts
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present disclosure provides a transistor device and a semiconductor layout structure. The transistor device includes an active region disposed in a substrate, a gate structure disposed over the active region, and a source/drain region disposed at two opposite sides of the gate structure. The active region includes a first region including a first length, a second region including a second length less than the first length, and a third region between the first region and the second region. The gate structure includes a first portion extending in a first direction and a second portion extending in a second direction perpendicular to the first direction. The first portion is disposed over at least the third region of the active region, and the second portion is disposed over at least a portion of the third region and a portion of the second region.

## Claims

### Claim 1

A transistor device comprising:
an active region disposed in a substrate, the active region comprising a first region comprising a first length, a second region comprising a second length, and a third region between the first region and the second region, wherein the first length is greater than the second length;
a gate structure disposed over the active region, the gate structure comprising:
a first portion extending in a first direction and disposed over at least the third region of the active region; and
a second portion extending in a second direction perpendicular to the first direction and disposed over at least a portion of the third region and a portion of the second region; and
a source/drain region disposed at two opposite sides of the gate structure.

### Claim 2 (depends on 1)

The transistor device of claim 1, wherein the first region comprises a first boundary and a second boundary, wherein the first boundary and the second boundary extend in the second direction, the second region comprises a third boundary and a fourth boundary, wherein the third boundary and the fourth boundary extend in the second direction, and the third region comprises a fifth boundary and a sixth boundary, wherein the fifth boundary extends in the second direction.

### Claim 3 (depends on 2)

The transistor of claim 2, wherein the first length of the first region is defined by a distance between the first boundary and the second boundary, and the second length of the second region is defined by a distance between the third boundary and the fourth boundary.

### Claim 4 (depends on 2)

The transistor device of claim 2, wherein the fifth boundary of the third region is in contact with the first boundary of the first region and the third boundary of the second region, and the sixth boundary of the third region is in contact with the second boundary of the first region and the fourth boundary of the second region.

### Claim 5 (depends on 4)

The transistor device of claim 4, wherein the sixth boundary of the third region extends in a third direction between the first direction and the second direction.

### Claim 6 (depends on 4)

The transistor device of claim 4, wherein a distance between a point on the fifth boundary of the third region and a point on the sixth boundary of the third region defines a third length equal to the first length of the first region, and a distance between another point on the firth boundary of the third region and another point on the sixth boundary of the third region defines a fourth length equal to the second length of the second region.

### Claim 7 (depends on 2)

The transistor of claim 2, wherein the first portion of the gate structure overlaps the sixth boundary of the third region.

### Claim 8 (depends on 2)

The transistor device of claim 2, wherein the second portion of the gate structure overlaps the sixth boundary of the third region.

### Claim 9 (depends on 1)

The transistor device of claim 1, wherein the first portion of the gate structure further overlaps a portion of the second region of the active region.

### Claim 10 (depends on 1)

The transistor device of claim 1, wherein the gate structure further comprises a third portion, and the second portion and the third portion are disposed at two opposite ends of the first portion and are both physically in contact with the first portion.

### Claim 11 (depends on 9)

The transistor device of claim 9, wherein the third portion of the gate structure overlaps the third region and a portion of the second region.

### Claim 12 (depends on 1)

The transistor device of claim 1, wherein the source region is disposed in the first region, and the drain region is disposed in the second region.

### Claim 13

A semiconductor layout structure comprising:
an active region surrounded by an isolation structure, the active region comprising:
two first regions comprising a first length;
a second region disposed between the two first regions, the second region comprising a second length less than the first length;
a third region disposed between one of the first regions and the second region; and
a fourth region disposed between the other of the first regions and the second region;
at least one first gate structure disposed over the active region and the isolation structure, the first gate structure comprising a first portion and a second portion perpendicular to each other;
at least one second gate structure disposed over the active region and the isolation structure, the second gate structure comprising a third portion parallel to the first portion and a fourth portion parallel to the second portion; and
a plurality of source/drain regions disposed in the active region,
wherein the second portion of the first gate structure overlaps the third region and a portion of the second region, and the fourth portion of the second gate structure overlaps the fourth region and a portion of the second region.

### Claim 14 (depends on 13)

The semiconductor layout structure of claim 13, wherein the first gate structure and the second gate structure are point symmetrical with respect to a central point.

### Claim 15 (depends on 13)

The semiconductor layout structure of claim 13, wherein the first portion of the first gate structure and the third portion of the second gate structure comprise a first distance therebetween, the first portion of the first gate structure and the fourth portion of the second gate structure comprise a second distance therebetween, the second portion of the first gate structure and the third portion of the second gate structure comprise a third distance therebetween, the first distance is greater than the second distance, the first distance is greater than the third distance, and the second distance is equal to the third distance.

### Claim 16 (depends on 13)

The semiconductor layout structure of claim 13, wherein the first portion of the first gate structure overlaps the third region, and the third portion of the second gate structure overlaps the fourth region.

### Claim 17 (depends on 16)

The semiconductor layout structure of claim 16, wherein the first portion of the first gate structure overlaps a slanted boundary of the third region, and the fourth portion of the second gate structure overlaps a slanted boundary of the fourth region.

### Claim 18 (depends on 13)

The semiconductor layout structure of claim 13, wherein the first gate structure further comprises a fifth portion overlapping the third region and a portion of the second region, and the second gate structure further comprises a sixth portion overlapping the fourth region and a portion of the second region.

### Claim 19 (depends on 18)

The semiconductor layout structure of claim 18, wherein the first gate structure and the second gate structure are line symmetrical with respect to a central line, the two first regions are line symmetrical with respect to a central line, and the third region and the fourth region are line symmetrical with respect to a central line.

### Claim 20 (depends on 18)

The semiconductor layout structure of claim 18, wherein the first portion of the first gate structure and the third portion of the second gate structure comprise a first distance therebetween, the second portion of the first gate structure and the sixth portion of the second gate structure comprise a second distance therebetween, the fifth portion of the first gate structure and the fourth portion of the second gate structure comprise a third distance therebetween, the first distance is greater than the second distance, the first distance is greater than the third distance, and the second distance is equal to the third distance.