# US 2019/0172907 A1 · Isolation of circuit elements using front side deep trench etch

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- Number: US 2019/0172907 A1
- Document ID: US20190172907A1
- Status: Published application
- Kind: A1
- Application number: 16/266,677
- Filed: 2019-02-04
- Published: 2019-06-06
- Earliest claimed: 2015-10-27
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Dan Carothers; Ricky Jackson; Rajarshi Mukhopadhyay; Ben Cook
- Web page: https://patentgrep.com/patent/US20190172907A1

## CPC

- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 1/00: Resistors, capacitors or inductors
- H10D 1/68: Capacitors having no potential barriers
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/217: {comprising ring-shaped isolation structures outside of the via holes}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/496: {Capacitor integral with wiring layers}
- H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5453: {connecting between multiple bond pads on a chip, e.g. daisy chain}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit is formed by forming an isolation trench through at least a portion of an interconnect region, at least 40 microns deep into a substrate of the integrated circuit, leaving at least 200 microns of substrate material under the isolation trench. Dielectric material is formed in the isolation trench at a substrate temperature no greater than 320° C. to form an isolation structure which separates an isolated region of the integrated circuit from at least a portion of the substrate. The isolated region contains an isolated component. The isolated region of the integrated circuit may be a region of the substrate, and/or a region of the interconnect region. The isolated region may be a first portion of the substrate which is laterally separated from a second portion of the substrate. The isolated region may be a portion of the interconnect region above the isolation structure.

## Claims

### Claim 1

A method of forming an integrated circuit, the method comprising:
providing a substrate comprising semiconductor material;
forming components at a top surface of the substrate;
forming an interconnect region over the substrate, comprising forming dielectric layers and forming interconnects in the dielectric layers;
forming an isolation trench through at least a portion of the interconnect region and into the substrate at least 40 microns deep, so that at least 200 microns of substrate material remains in the substrate under the isolation trench, the at least a portion of the interconnect region containing at least a portion of the interconnects; and
forming dielectric material in the isolation trench to form an isolation structure, the dielectric material contacting the substrate and the interconnect region, the isolation structure separating an isolated region of the integrated circuit from at least a portion of the substrate, the isolated region containing an isolated component of the integrated circuit.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the dielectric material in the isolation trench comprises providing the dielectric material into the isolation trench using a process selected from the group consisting of an inkjet process, a spin-coat process, a force fill process and a vapor transfer process.

### Claim 3 (depends on 1)

The method of claim 1, wherein the dielectric material is selected from the group consisting of an organic polymer, a silicone polymer, an organic silane, a sol gel and a ceramic slurry.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming the dielectric material in the isolation trench comprises:
providing a first dielectric material into a lower portion of the isolation trench; and
providing a second dielectric material into an upper portion of the isolation trench above the first material.

### Claim 5 (depends on 1)

The method of claim 1, comprising curing the dielectric material in the isolation trench at a temperature no greater than 320° C.

### Claim 6 (depends on 1)

The method of claim 1, wherein forming the isolation trench comprises:
forming a layer of hard mask material;
forming an isolation mask comprising photoresist over the layer of hard mask material by a photolithographic process, the isolation mask exposing the layer of hard mask material in an area for the isolation trench;
removing hard mask material from the layer of hard mask material where exposed by the isolation mask to form a hard mask; and
removing dielectric material from the dielectric layers of the interconnect region and removing semiconductor material from the substrate, in an area exposed by the hard mask, to form the isolation trench.

### Claim 7 (depends on 6)

The method of claim 6, comprising removing the hard mask after the isolation trench is formed.

### Claim 8 (depends on 1)

The method of claim 1, comprising forming additional dielectric layers of the interconnect region over the isolation structure and forming interconnects in the additional dielectric layers.

### Claim 9 (depends on 8)

The method of claim 8, comprising forming the isolated component above the isolation structure in the additional dielectric layers of the interconnect region.

### Claim 10 (depends on 1)

The method of claim 1, comprising removing material from a bottom surface of the substrate to expose a bottom of the isolation.

### Claim 11

A method of forming an integrated circuit, the method comprising:
providing a substrate comprising semiconductor material;
forming components at a top surface of the substrate;
forming an interconnect region over the substrate, comprising forming dielectric layers and forming interconnects in the dielectric layers;
forming an isolation mask over the interconnect region, the isolation mask exposing an area for an isolation trench;
removing material from the interconnect region and the substrate in the area exposed by the isolation mask to form an isolation trench completely through the interconnect region and into the substrate at least 40 microns deep, so that at least 200 microns of substrate material remains in the substrate under the isolation trench; forming dielectric material in the isolation trench by an ink jet process at a substrate temperature no greater than 320° C. to form an isolation structure, the dielectric material contacting the substrate and the interconnect region, the isolation structure separating an isolated region of the integrated circuit from at least a portion of the substrate, the isolated region containing an isolated component of the integrated circuit; and
curing the dielectric material in the isolation trench at a substrate temperature no greater than 320° C.