# US 2019/0172903 A1 · Making electrical components in handle wafers of integrated circuit packages

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- Number: US 2019/0172903 A1
- Document ID: US20190172903A1
- Status: Published application
- Kind: A1
- Application number: 16/272,736
- Filed: 2019-02-11
- Published: 2019-06-06
- Earliest claimed: 2014-05-02
- Assignees: Invensas Corporation
- Applicants: Invensas Corporation
- Inventors: Liang Wang; Hong Shen; Rajesh Katkar
- Web page: https://patentgrep.com/patent/US20190172903A1

## CPC

- H10D 1/692: {Electrodes}
- H10D 1/68: Capacitors having no potential barriers
- H10D 1/694: {comprising noble metals or noble metal oxides}
- H10W 20/496: {Capacitor integral with wiring layers}
- H10W 70/095: {of vias therein}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/073: {of die-attach connectors}
- H10W 74/01: Manufacture or treatment
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 72/9226: {with via interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Each of a first and a second integrated circuit structures has hole(s) in the top surface, and capacitors at least partially located in the holes. A semiconductor die is attached to the top surface of the second structure. Then the first and second structures are bonded together so that the die becomes disposed in the first structure's cavity, and the holes of the two structures are aligned to electrically connect the respective capacitors to each other. A filler is injected into the cavity through one or more channels in the substrate of the first structure. Other embodiments are also provided.

## Claims

### Claim 1

A fabrication method comprising:
(a) obtaining a first integrated circuit structure comprising a first substrate comprising a bottom surface having a cavity, and comprising a first circuitry comprising one or more first capacitors each of which is at least partially located in a respective first hole formed in a top surface of the first substrate, each first capacitor comprising:
a first electroconductive layer formed within or upon an interior surface of the respective first hole;
a dielectric layer formed over the first electroconductive layer and at least partially located in the respective first hole;
a second electroconductive layer formed over the dielectric layer and at least partially located in the respective first hole;
(b) obtaining a second integrated circuit structure comprising a second substrate comprising a second circuitry comprising one or more second capacitors each of which is at least partially located in a respective second hole formed in a top surface of the second substrate, each second capacitor comprising:
a first electroconductive layer formed within or upon an interior surface of the respective second hole;
a dielectric layer formed over the first electroconductive layer and at least partially located in the respective second hole;
a second electroconductive layer formed over the dielectric layer and at least partially located in the respective second hole;
the second integrated circuit structure further comprising a semiconductor die attached to the top surface of the second substrate and electroconductively coupled to the second circuitry;
(c) after obtaining the first and second integrated circuit structures, positioning the first and second integrated circuit structures to align each first hole with a corresponding second hole, and bonding the first integrated structure to the second integrated structure, the bonding comprising bonding the first substrate to the second substrate, wherein in said bonding of the first and second integrated structures, for each aligned pair of a first hole and
a second hole, the first electroconductive layer of the respective first capacitor becomes electroconductively coupled to the second electroconductive layer of the respective second capacitor;
wherein at a conclusion of said bonding of the first and second integrated circuit structures, the semiconductor die is disposed in the cavity but is spaced from the first substrate to define a headspace between the cavity surface and the semiconductor die surface;
wherein the method further comprises injecting a filler into the headspace through one or more channels in the first substrate that communicate between the cavity and the top surface of the first substrate.