# US 2019/0172902 A1 · Semiconductor Device and Method of Forming Substrate Including Embedded Component with Symmetrical Structure

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- Number: US 2019/0172902 A1
- Document ID: US20190172902A1
- Status: Published application
- Kind: A1
- Application number: 16/267,142
- Filed: 2019-02-04
- Published: 2019-06-06
- Earliest claimed: 2015-05-27
- Assignees: STATS ChipPAC Pte. Ltd.
- Applicants: STATS ChipPAC Pte. Ltd.
- Inventors: JinHee Jung; HyungSang Park; SungSoo Kim
- Web page: https://patentgrep.com/patent/US20190172902A1

## CPC

- H10D 1/68: Capacitors having no potential barriers
- H05K 1/185: associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/614: {the multiple chips being integrally enclosed}
- H05K 3/4664: {Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders (H05K3/4647 takes precedence)}
- H05K 2201/10015: Non-printed capacitor
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 70/095: {of vias therein}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/635: {Through-vias}
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/9413: {on encapsulations}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device comprises a first conductive layer. A second conductive layer is formed over the first conductive layer. A semiconductor component is disposed over the first conductive layer. The second conductive layer lies in a plane between a top surface of the semiconductor component and a bottom surface of the semiconductor component. A third conductive layer is formed over the semiconductor component opposite the first conductive layer. The semiconductor device includes a symmetrical structure. A first insulating layer is formed between the first conductive layer and semiconductor component. A second insulating layer is formed between the semiconductor component and third conductive layer. A height of the first insulating layer between the first conductive layer and semiconductor component is between 90% and 110% of a height of the second insulating layer between the semiconductor component and third conductive layer. The semiconductor component includes a passive device.

## Claims

### Claim 1

A method of making a semiconductor device, comprising:
forming a first insulating layer;
forming a second insulating layer over the first insulating layer;
forming a first conductive layer over the second insulating layer;
disposing an electrical component on the first insulating layer in an opening of the second insulating layer;
forming a third insulating layer over the electrical component;
forming a first conductive via through the first insulating layer and extending to a terminal of the electrical component; and
forming a second conductive via through the third insulating layer and extending to the terminal of the electrical component.

### Claim 2 (depends on 1)

The method of claim 1, further including disposing the electrical component within a height of the first conductive layer.

### Claim 3 (depends on 1)

The method of claim 1, further including:
providing a carrier;
forming the first insulating layer directly on the carrier; and
removing the carrier.

### Claim 4 (depends on 1)

The method of claim 1, wherein the second conductive via is vertically aligned over the first conductive via.

### Claim 5 (depends on 1)

The method of claim 1, further including:
forming a third conductive via through the first insulating layer and extending to the first conductive layer; and
forming a fourth conductive via through the third insulating layer and extending to the first conductive layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the fourth conductive via is vertically aligned over the third conductive via.

### Claim 7

A method of making a semiconductor device, comprising:
forming a first insulating layer;
disposing an electrical component over the first insulating layer;
forming a second insulating layer over the electrical component;
forming a first conductive via through the first insulating layer extending to a terminal of the electrical component; and
forming a second conductive via through the second insulating layer extending to the terminal of the electrical component.

### Claim 8 (depends on 7)

The method of claim 7, further including forming the semiconductor device to include a vertically symmetrical structure.

### Claim 9 (depends on 7)

The method of claim 7, wherein the first conductive via and second conductive via are vertically aligned.

### Claim 10 (depends on 7)

The method of claim 7, further including:
forming a conductive layer over the first insulating layer;
forming a third insulating layer over the conductive layer;
forming an opening in the third insulating layer to expose the conductive layer;
removing the conductive layer after forming the opening; and
disposing the electrical component in the opening after removing the conductive layer.

### Claim 11 (depends on 7)

The method of claim 7, further including:
forming a conductive layer over the first insulating layer;
forming a third conductive via through the first insulating layer to the conductive layer; and
forming a fourth conductive via through the second insulating layer to the conductive layer, wherein the third conductive via and fourth conductive via are vertically aligned.

### Claim 12 (depends on 7)

The method of claim 7, further including:
providing a first conductive layer;
forming the first insulating layer over the first conductive layer;
forming a first opening through the first conductive layer and first insulating layer;
forming the first conductive via in the first opening;
forming a second conductive layer over the second insulating layer;
forming a second opening through the second conductive layer and second insulating layer; and
forming the second conductive via in the second opening.

### Claim 13 (depends on 12)

The method of claim 12, further including;
forming the first opening to expose the terminal of the electrical component; and
forming the second opening to expose the terminal of the electrical component.

### Claim 14

A method of making a semiconductor device, comprising:
forming a substrate including an electrical component embedded in the substrate;
forming a first conductive via through a first surface of the substrate to a terminal of the electrical component; and
forming a second conductive via through a second surface of the substrate to the terminal of the electrical component.

### Claim 15 (depends on 14)

The method of claim 14, further including forming the substrate with the electrical component centered vertically within the substrate.

### Claim 16 (depends on 14)

The method of claim 14, further including forming a first conductive layer centered vertically within the substrate.

### Claim 17 (depends on 14)

The method of claim 14, further including:
forming a second conductive layer on the second surface of the substrate; and
forming a third conductive layer on the first surface of the substrate.

### Claim 18 (depends on 17)

The method of claim 17, further including:
forming the first conductive via through the third conductive layer; and
forming the second conductive via through the second conductive layer.

### Claim 19 (depends on 14)

The method of claim 14, further including:
forming a third conductive via through the first surface of the substrate to a second terminal of the electrical component; and
forming a fourth conductive via through the second surface of the substrate to the second terminal of the electrical component.

### Claim 20

A semiconductor device, comprising:
a substrate including an electrical component embedded in the substrate;
a first conductive via formed through a first surface of the substrate to a terminal of the electrical component; and
a second conductive via formed through a second surface of the substrate to the terminal of the electrical component.

### Claim 21 (depends on 20)

The semiconductor device of claim 20, wherein the electrical component is centered vertically within the substrate.

### Claim 22 (depends on 20)

The semiconductor device of claim 20, further including:
a third conductive via formed through the first surface of the substrate to a second terminal of the electrical component; and
a fourth conductive via formed through the second surface of the substrate to the second terminal of the electrical component.

### Claim 23 (depends on 20)

The semiconductor device of claim 20, further including a first conductive layer centered vertically within the substrate.

### Claim 24 (depends on 20)

The semiconductor device of claim 20, further including:
a second conductive layer formed on the second surface of the substrate; and
a third conductive layer formed on the first surface of the substrate.

### Claim 25 (depends on 24)

The semiconductor device of claim 24, wherein the first conductive via is formed through the third conductive layer and the second conductive via is formed through the second conductive layer.