# US 2019/0172901 A1 · Semiconductor Resistor Structure And Method For Making > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0172901 A1 - Document ID: US20190172901A1 - Status: Published application - Kind: A1 - Application number: 16/254,223 - Filed: 2019-01-22 - Published: 2019-06-06 - Earliest claimed: 2016-12-30 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Mattias Erik Dahlström; Li Jen Choi - Web page: https://patentgrep.com/patent/US20190172901A1 ## CPC - H10D 1/47: Resistors having no potential barriers - H10D 1/474: {comprising refractory metals, transition metals, noble metals, metal compounds or metal alloys, e.g. silicides} - H10P 14/414: {of metal-silicide materials} - H10P 14/416: {of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers} - H10P 76/204: {of organic photoresist masks} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Disclosed examples include a resistor comprising a semiconductor structure having a length dimension with first and second ends spaced from one another and an intermediate region between the first and second ends, first and second metal-semiconductor compound structures on the semiconductor structure proximate the first and second ends of the semiconductor structure, the first and second metal-semiconductor compound structures being spaced apart from each other along the length dimension of the semiconductor structure, and at least one intermediate metal-semiconductor compound structure on a portion of the intermediate region of the semiconductor structure between the first and second ends, the intermediate metal-semiconductor compound structure being spaced apart from the first and second metal-semiconductor compound structures on the semiconductor structure. ## Claims ### Claim 1 An integrated circuit, comprising: a polysilicon structure having a length dimension with first and second ends spaced from one another and an intermediate region between the first and second ends; first and second doped regions within the polysilicon structure proximate the first and second ends of the polysilicon structure; first and second metal-semiconductor compound structures on the polysilicon structure proximate the first and second ends of the polysilicon structure, the first and second metal-semiconductor compound structures being spaced apart from each other along the length dimension of the polysilicon structure; and at least one intermediate metal-semiconductor compound structure on a portion of the intermediate region of the polysilicon structure between the first and second ends, the intermediate metal-semiconductor compound structure having a depth less than a depth of the first and second doped regions. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein the polysilicon structure includes silicon, and wherein the metal-semiconductor compound includes a silicide. ### Claim 3 (depends on 2) The integrated circuit of claim 2, wherein the silicide includes cobalt, titanium, nickel or nickel-platinum silicide. ### Claim 4 (depends on 1) The integrated circuit of claim 1, wherein the polysilicon structure is doped. ### Claim 5 (depends on 1) The integrated circuit of claim 1, comprising a plurality of metal-semiconductor structures spaced apart from one another and from the first and second metal-semiconductor structures along the intermediate region of the polysilicon structure. ### Claim 6 (depends on 5) The integrated circuit of claim 5, wherein the plurality of metal-semiconductor structures are evenly spaced apart from one another, ### Claim 7 (depends on 1) The integrated circuit of claim 1, wherein the first and second metal-semiconductor structures and the at least one intermediate metal-semiconductor structure extend across a width of the polysilicon structure. ### Claim 8 (depends on 7) The integrated circuit of claim 7, wherein the first and second metal-semiconductor structures and the at least one intermediate metal-semiconductor structure are coextensive across a width of the polysilicon structure. ### Claim 9 A method of fabricating an integrated circuit, the method comprising: forming a polysilicon structure on a substrate, the polysilicon structure including first and second ends spaced from one another and an intermediate region between the first and second ends; forming first and second doped regions within the polysilicon structure proximate the first and second ends of the polysilicon structure; forming first and second silicide structures on the polysilicon structure proximate the first and second ends of the polysilicon structure, the first and second silicide structures being spaced apart from each other on the polysilicon structure; and forming at least one intermediate silicide structure on a portion of the intermediate region of the polysilicon structure between the first and second ends, the intermediate metal-semiconductor compound structure having a depth less than a depth of the first and second doped regions. ### Claim 10 (depends on 9) The method of claim 9, wherein the forming the first and second silicide structures on the first and second ends of the polysilicon structure includes: depositing a silicide block layer over the polysilicon structure; patterning the silicide block layer to expose the first and second ends of the polysilicon structure and to expose at least one intermediate portion of the intermediate region spaced from the first and second ends; depositing a metal layer over the polysilicon structure and remaining silicide block layer; and annealing the metal layer and the exposed portions of the polysilicon structure to form silicide at an interface of the metal layer and the polysilicon structure. ### Claim 11 (depends on 10) The method of claim 10, wherein patterning the silicide block layer includes: depositing a photoresist layer over the silicide block layer; patterning the photoresist layer to expose at least a portion of the silicide block layer above the first and second ends of the polysilicon structure at locations which the first and second silicide structures are to be formed, and to expose the intermediate portion of the intermediate region spaced from the first and second ends at which the intermediate silicide structure is to be formed; removing the exposed portions of the silicide block layer using the photoresist as a mask to expose the first and second ends of the polysilicon layer and to expose the intermediate portion of the intermediate region; and removing the photoresist. ### Claim 12 (depends on 9) The method of claim 9, wherein the first and second silicide end regions and the at least one intermediate silicide region are formed concurrently. ### Claim 13 An integrated circuit, comprising: a resistor region of a semiconductor substrate, the resistor region having a length dimension with first and second ends spaced from one another and an intermediate region between the first and second ends; an oxide structure formed on or in the semiconductor substrate surrounding the resistor region of the semiconductor substrate; first and second doped regions within the semiconductor substrate proximate the first and second ends of the semiconductor substrate; first and second metal-semiconductor compound structures on the first and second ends of the resistor region, the first and second metal-semiconductor compound structures being spaced apart from each other along the length dimension of the resistor region; and at least one intermediate metal-semiconductor compound structure on a portion of the intermediate region of the resistor region between the first and second ends, the intermediate metal-semiconductor compound structure having a depth less than a depth of the first and second doped regions. ### Claim 14 (depends on 13) The integrated circuit of claim 13, wherein the semiconductor substrate includes silicon, and wherein the metal-semiconductor compound includes a silicide. ### Claim 15 (depends on 14) The integrated circuit of claim 14, wherein the silicide includes cobalt silicide. ### Claim 16 (depends on 14) The integrated circuit of claim 14, wherein the semiconductor substrate includes monocrystalline silicon. ### Claim 17 (depends on 14) The integrated circuit of claim 14, wherein the semiconductor substrate includes epitaxial silicon. ### Claim 18 (depends on 13) The integrated circuit of claim 13, wherein the at least one intermediate metal-semiconductor structure includes a plurality of metal-semiconductor structures spaced apart from one another and from the first and second metal-semiconductor structures along the length of the resistor region. ### Claim 19 (depends on 18) The integrated circuit of claim 18, wherein the plurality of metal-semiconductor structures are evenly spaced apart from one another. ### Claim 20 (depends on 18) The integrated circuit of claim 18, wherein the first and second metal-semiconductor structures and the at least one intermediate metal-semiconductor structure extend across a width of the resistor region.