# US 2019/0172864 A1 · Semiconductor package and related methods

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- Number: US 2019/0172864 A1
- Document ID: US20190172864A1
- Status: Published application
- Kind: A1
- Application number: 15/831,697
- Filed: 2017-12-05
- Published: 2019-06-06
- Earliest claimed: 2017-12-05
- Assignees: Semiconductor Components Industries, LLC
- Applicants: Semiconductor Components Industries, LLC
- Inventors: Shou-Chian HSU
- Web page: https://patentgrep.com/patent/US20190172864A1

## CPC

- H10F 39/026: {Wafer-level processing}
- H10F 39/024: {of coatings or optical elements}
- H10F 39/804: {Containers or encapsulations}
- H10P 72/74: {using temporarily an auxiliary support}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/656: Fan-in layouts
- H10W 72/01204: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/0198: {batch processes}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/331: {Shapes of die-attach connectors}
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Implementations of image sensor packages may include an image sensor chip, a first layer including an opening therethrough coupled to a first side of the image sensor chip, and a optically transmissive cover coupled to the first layer. The optically transmissive cover, the first layer, and the image sensor chip may form a cavity within the image sensor. The image sensor package may also include at least one electrical contact coupled to a second side of the image sensor chip opposing the first side and an encapsulant coating an entirety of the sidewalls of the image sensor package.

## Claims

### Claim 1

An image sensor package comprising:
an image sensor chip;
a first layer comprising an opening therethrough coupled to a first side of the image sensor chip;
an optically transmissive cover coupled to the first layer, wherein the optically transmissive cover, the first layer, and the image sensor chip comprise a cavity within the image sensor package;
at least one electrical contact coupled to a second side of the image sensor chip opposing the first side; and
an encapsulant coating an entirety of the sidewalls of the image sensor package;
wherein a perimeter of the optically transmissive cover is the same size as a perimeter of the first side of the image sensor chip.

### Claim 2 (depends on 1)

The package of claim 1, further comprising a redistribution layer covering the second side of the image sensor chip.

### Claim 3 (depends on 1)

The package of claim 1, wherein the encapsulant comprises a solder mask.

### Claim 4 (depends on 1)

The package of claim 1, wherein the at least one electrical contact is a bump.

### Claim 5 (depends on 1)

The package of claim 1, wherein the encapsulant crosses all of the interfaces on the sidewalls of the package.

### Claim 6 (depends on 1)

The package of claim 1, wherein the encapsulant substantially covers five sides of the package.

### Claim at position 7

-20. (canceled)

### Claim 21

An image sensor package comprising:
an image sensor chip;
a first layer comprising a plurality of dams coupled to a first side of the image sensor chip;
an optically transmissive cover coupled to the plurality of dams, wherein the optically transmissive cover, the plurality of dams, and the image sensor chip comprise a cavity within the image sensor package;
a redistribution layer covering the second side of the image sensor chip;
at least one electrical contact coupled to a second side of the image sensor chip opposing the first side; and
an encapsulant coating an entirety of the sidewalls of the image sensor package;
wherein the encapsulant is a single encapsulant substantially covering five sides of the package.

### Claim 22 (depends on 21)

The package of claim 21, wherein the encapsulant comprises a solder mask.

### Claim 23 (depends on 21)

The package of claim 21, wherein the at least one electrical contact is a bump.

### Claim 24 (depends on 21)

The package of claim 21, wherein the encapsulant crosses all of the interfaces on the sidewalls of the package.

### Claim 25

(canceled)