# US 2019/0172860 A1 · Electromagnetic radiation detector comprising charge transport across a bonded interface

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- Number: US 2019/0172860 A1
- Document ID: US20190172860A1
- Status: Published application
- Kind: A1
- Application number: 16/324,125
- Filed: 2017-08-29
- Published: 2019-06-06
- Earliest claimed: 2016-08-31
- Assignees: G-ray Switzerland SA
- Applicants: G-ray Switzerland SA
- Inventors: Hans VON KÄNEL
- Web page: https://patentgrep.com/patent/US20190172860A1

## CPC

- H10F 39/018: {of hybrid image sensors}
- H10F 39/021: {of image sensors having active layers comprising only Group III-V materials, e.g. GaAs, AlGaAs or InP}
- H10F 39/026: {Wafer-level processing}
- H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
- H10F 39/189: {X-ray, gamma-ray or corpuscular radiation imagers}
- H10F 39/1895: {of the hybrid type}
- H10F 39/195: {X-ray, gamma-ray or corpuscular radiation imagers}
- H10F 39/809: {of hybrid image sensors}
- H10H 29/142: {Two-dimensional arrangements, e.g. asymmetric LED layout}
- H10W 90/00: Package configurations
- H10F 39/022: {of image sensors having active layers comprising only Group II-VI materials, e.g. CdS, ZnS or CdTe}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Monolithic CMOS integrated pixel detector (10, 20, 30, 260, 470, 570), and systems and methods are provided for the detection and imaging of electromagnetic radiation with high spectral and spatial resolution. Such detectors comprise a Si wafer with a CMOS processed readout bonded to an absorber wafer in an electrically conducting covalent wafer bond. The pixel detectors, systems and methods are used in various medical and non-medical types of applications.

## Claims

### Claim 1

A monolithic CMOS integrated pixel detector (10, 20, 30, 260, 470, 570) for the detection of electromagnetic radiation, comprising
a. a silicon readout wafer (11, 21, 31, 41, 120, 130, 165, 215, 415, 515) with at least one layer (127, 167, 217, 417, 517) doped to have a first conduction type, the layer comprising CMOS processed readout electronics;
b. implants for charge collectors (15, 25, 35, 45, 123, 223, 423, 523) doped to have the first conduction type, the implants communicating with the readout electronics and defining detector pixels;
c. an absorber wafer (16, 26, 36, 46, 220, 481, 541′) made from material comprising at least a second conduction type and a metallic back contact (19, 29, 39, 49, 262, 472, 572); and,
d. contact pads (124, 254, 464, 564) communicating with an external printed circuit board;
wherein the silicon wafer and the absorber wafer are covalently bonded to form a monolithic unit; and wherein the monolithic unit comprises a p-n junction formed by a layer of the first conduction type and a layer of the second conduction type; and wherein charge collectors are disposed to receive the electrical charges crossing the bonded interface; and wherein registered charges are processed by a processor typically for diagnostic purposes.

### Claim 2 (depends on 1)

The detector of claim 1, wherein further, the depletion region of the p-n junction is disposed to extend across the bonding interface (17, 27, 37, 237, 437, 537) to separate electron-hole pairs into charges travelling in opposite directions when the electron-hole pairs are generated by electromagnetic radiation absorbed in the absorber wafer and when a reverse bias is applied to the back contact.

### Claim 3 (depends on 1)

The detector of claim 1, wherein the readout electronics is disposed to convert said electrical charges into digital signals which can pass through contact pads (124, 254, 464, 564) to the external printed circuit board to be stored, processed and/or displayed as images on a computer screen.

### Claim 4 (depends on 1)

The detector of claim 1, wherein the absorber wafer (16, 26, 36, 46, 220, 481, 541′) is made from single crystal material.

### Claim 5

The monolithic CMOS integrated pixel detector of any of the above claims, wherein the p-n junction (18) is located at the bonded interface (17, 27, 37, 237, 437, 537).

### Claim 6 (depends on 1, 2, 3, 4)

The monolithic CMOS integrated pixel detector of any of claims 1 to 4, wherein the silicon readout wafer (11, 21, 31, 120, 130, 165, 215, 415, 515) comprises a high resistivity layer (127′, 167′, 217′, 417′, 517′) doped to have the second conduction type, and wherein the p-n junction (28) is located within the silicon readout wafer (11, 21, 31, 120, 130, 165, 215, 415, 515).

### Claim 7 (depends on 1, 2, 3, 4)

The monolithic CMOS integrated pixel detector of any of claims 1 to 4, wherein the absorber wafer (46, 220, 381, 481, 541′) comprises a layer (51, 224, 319′, 425′, 533) of the first conduction type, and wherein the p-n junction is located within the absorber wafer (220, 381, 481, 541′).

### Claim 8

The monolithic CMOS integrated pixel detector of any of the above claims, wherein the pixel size is defined by the spacing of the implants for charge collectors.

### Claim 9 (depends on 8)

The monolithic CMOS integrated pixel detector of claim 8, wherein the pixel size is selected from one of a list of ranges, consisting of 5-20 μm, 20-50 μm, 50-100 μm and 100-200 μm.

### Claim 10 (depends on 1, 2, 3, 4, 5, 6, 7, 8, 9)

The monolithic CMOS integrated pixel detector of any of claims 1 to 9, wherein the readout wafer has a thickness of about 10-100 μm.

### Claim 11 (depends on 1, 2, 3, 4, 5, 6, 7, 8, 9)

The monolithic CMOS integrated pixel detector of any of claims 1 to 9, wherein the readout wafer has a thickness of 10-50 μm.

### Claim 12 (depends on 1, 2, 3, 4, 5, 6, 7, 8, 9)

The monolithic CMOS integrated pixel detector of any of claims 1 to 9, wherein the readout wafer has a thickness of 10-20 μm.

### Claim 13 (depends on 1)

The monolithic CMOS integrated pixel detector of claim 1, wherein the at least one doped layer (127, 167, 217, 417, 517) of the readout wafer is a high resistivity layer with a resistivity selected from one of a list of ranges consisting of 1-2 kΩcm, 2-5 kΩcm and 5-50 kΩcm.

### Claim 14 (depends on 6)

The monolithic CMOS integrated pixel detector of claim 6, wherein the layer (127′, 167′, 217′, 417′, 517′) of the readout wafer has a resistivity selected from one of a list of ranges consisting of 1-2 kΩcm, 2-5 kΩcm and 5-50 kΩcm.

### Claim 15 (depends on 1)

The monolithic CMOS integrated pixel detector of claim 1, wherein the absorber wafer comprises a material selected from one of the group of materials consisting of Si, SiC, Ge, a SiGe alloy, GaAs, CdTe, a CdZnTe alloy, GaN, a AlGaN alloy, a InGaN alloy, and a AlInGaN alloy.

### Claim 16 (depends on 1)

The monolithic CMOS integrated pixel detector of claim 1, wherein the absorber wafer comprises an epitaxial absorption layer on a silicon substrate.

### Claim 17 (depends on 16)

The monolithic CMOS integrated pixel detector of claim 16, wherein the silicon substrate has a resistivity selected from one of a list of ranges consisting of 1-2 kΩcm, 2-5 kΩcm and 5-50 kΩcm.

### Claim 18 (depends on 16, 17)

The monolithic CMOS integrated pixel detector of any of claim 16 or 17, wherein the silicon substrate comprises a thickness within range of thicknesses selected from one of a list of ranges consisting of 10-30 μm and 15-20 μm.

### Claim 19 (depends on 16, 17, 18)

The monolithic CMOS integrated pixel detector of any one of claims 16 to 18, wherein the Si substrate is patterned in the form of pillars separated by trenches, wherein the pillar width is selected from one of a group of widths consisting of 1-100 μm and 2-20 μm, and wherein the width of trenches are selected from one of a group of widths consisting of 2-6 μm and 3-5 μm.

### Claim 20 (depends on 16, 17, 18, 19)

The monolithic CMOS integrated pixel detector of any one of claims 16 to 19, wherein the epitaxial absorption layer is a SiGe alloy layer.

### Claim 21 (depends on 20)

The monolithic CMOS integrated pixel detector of claim 20, wherein the SiGe alloy layer is pixelated.

### Claim 22 (depends on 21)

The monolithic CMOS integrated pixel detector of claim 21, wherein the pixelated SiGe alloy layer has a Ge content of between 20 and 80%.

### Claim 23 (depends on 21)

The monolithic CMOS integrated pixel detector of claim 21, wherein the pixelated SiGe alloy layer has a Ge content of between 70 and 80%.

### Claim 24 (depends on 21)

The monolithic CMOS integrated pixel detector of claim 21, wherein the pixelated SiGe alloy layer is compositionally graded up to a final Ge content.

### Claim 25 (depends on 24)

The monolithic CMOS integrated pixel detector of claim 24, wherein the final Ge content is a content selected from one of a range of contents consisting of 20-80% and 70-80%.

### Claim 26 (depends on 16)

The monolithic CMOS integrated pixel detector of claim 16, wherein the epitaxial absorption layer is a Ge layer width a thickness within a range of thicknesses selected from one of a list of ranges consisting of 0.5-1.5 μm, 0.4-1.0 μm and 0.2-0.5 μm.

### Claim 27 (depends on 20, 21, 22, 23, 24, 25)

The monolithic CMOS integrated pixel detector of any one of claims 20 to 25, wherein the epitaxial absorption layer has a thickness of between 100 and 300 μm.

### Claim 28

A method for forming a monolithic CMOS integrated pixel detector for the detection of electromagnetic radiation, the method comprising the steps of:
a. providing a silicon wafer comprising at least one doped Si layer (117, 127, 167, 217, 417, 517) doped to have a first conduction type;
b. forming a readout wafer (120, 215, 415, 515) with a field oxide (125, 216, 416, 516) by CMOS processing a readout electronics in the at least one doped Si layer (117, 127, 167, 217, 417, 517);
c. forming implants for charge collectors (15, 25, 35, 45, 123, 223, 423, 523) doped to have the first conduction type, the implants communicating with the readout electronics and defining detector pixels;
d. forming contact pads (124, 254, 464, 564) to connect the readout electronics to a printed circuit board of the outside world;
e. providing an absorber wafer (16, 26, 36, 46, 220, 381, 481, 541′) comprising at least a layer of a second conduction type;
f. forming a low-temperature covalent bond (17, 27, 37, 47, 237, 437, 537) between the readout wafer and the absorber wafer;
g. forming a metallic back contact (262, 472, 572) on the surface (221, 442, 543) of the absorber wafer (220, 481, 541′);
wherein the layers of the first conduction type and the layers of the second conduction type are disposed to form a p-n junction, the depletion region of which extends across the bonding interface (17, 27, 37, 47, 237, 437, 537) when a reverse bias is applied to the metallic back contact, thereby separating electron-hole pairs into charges travelling in opposite directions when generated by electromagnetic radiation absorbed in the absorber wafer; and wherein the charge collectors are disposed to receive the electrical charges crossing the bonded interface; and wherein the readout electronics is disposed to convert said electrical charges into digital signals which can be transmitted through contact pads (124, 254, 464, 564) to an external printed circuit board and further stored, processed and displayed as images on a computer screen.

### Claim 29 (depends on 28)

The method of claim 28, wherein forming said low-temperature covalent bond (17, 27, 37, 47, 237, 437, 537) between the readout wafer and the absorber wafer comprises steps of:
a. planarizing the readout wafer (130, 165, 215, 415, 515) by planarizing its oxide surface (132) and rendering it essentially particle-free and activated for low-temperature oxide-to-oxide fusion bonding;
b. providing an oxidized Si carrier wafer (140, 213, 413, 513) and rendering its surface (143) essentially particle-free and plasma activated for low-temperature oxide-to-oxide fusion bonding;
c. forming a bonded wafer stack (150, 410, 510) by bonding the activated oxide surface (132) of the readout wafer onto the activated surface (143) of the carrier wafer in a low-temperature oxide-to-oxide wafer bond;
d. thinning the readout wafer (165, 215, 415, 515) bonded to the carrier wafer;
e. activating the surface (211, 411) of the readout wafer and the surface (222, 386, 422) of the absorber wafer by rendering them essentially oxide-free and damage-free by one of a list of steps consisting of HF dip and plasma activation;
f. removing the carrier wafer (140, 213, 413, 513) at least partially from the readout wafer (245, 415, 515) after forming said low-temperature covalent bond (17, 27, 37, 47, 237, 437, 537);
g. opening contact holes (252, 462, 562) to expose the electrical contact pads (124, 254, 464, 564) providing the electrical connections to the printed circuit board.

### Claim 30 (depends on 28)

The method of claim 28, wherein forming the monolithic CMOS integrated pixel detector comprises steps of:
a. providing a silicon-on-insulator (SOI) wafer; and
b. forming the readout wafer (120, 160, 210, 415, 515) by CMOS processing the readout electronics in the SOI wafer.

### Claim 31 (depends on 28, 29, 30)

The method of one of claims 28 to 30, wherein providing the absorber wafer comprises steps of:
a. providing a substrate wafer (310) from a list of wafers comprising at least a high resistivity silicon wafer and a silicon-on-insulator (SOI) wafer comprising a Si substrate (313), oxide box (314) and a high resistivity Si layer (317) of a thickness of 10-30 μm made up of at least one layer (319, 425) of the second conduction type;
b. patterning the Si layer in the form of pillars (328) separated by trenches (329);
c. growing an epitaxial absorption layer in the form of separated crystals (331, 441) of the second conduction type;
d. filling the trenches between Si pillars and epitaxial crystals with a filling material (349);
e. forming an oxide layer (351, 428) on the surface (332) of the epitaxial crystals (331);
f. planarizing the oxide layer (351, 428) and rendering its surface (352) particle-free and plasma activated for low-temperature oxide-to-oxide fusion bonding;
g. providing a carrier wafer (360, 426) made of oxidized Si or fused quartz and rendering its upper surface (362) particle-free and plasma activated for low-temperature oxide-to-oxide fusion bonding;
h. forming a strong oxide-to-oxide fusion bond (371, 424) between surface (352) of the absorber wafer and surface (362) of the carrier wafer; and
i. forming a thinned absorber wafer (381, 481) by removing the substrate wafer (310).

### Claim 32 (depends on 28, 29, 30)

The method of one of claims 28 to 30, wherein providing the absorber wafer comprises steps of:
a. providing a substrate wafer (310) from a list of wafers comprising at least a silicon wafer and a silicon-on-insulator (SOI) wafer comprising a Si substrate (313), oxide box (314) and a Si layer (317, 527) of a thickness of 10-30 μm;
b. patterning the Si layer in the form of pillars (328) separated by trenches (329);
c. growing an epitaxial absorption layer in the form of separated crystals (331, 541) of the second conduction type;
d. filling the trenches between Si pillars and epitaxial crystals with a filling material (349); and
e. planarizing the surface (522) of the epitaxial crystals.

### Claim 33 (depends on 1)

A system for near-infrared detection comprising the pixel detector of claim 1.

### Claim 34 (depends on 33)

The system of claim 33, wherein the pixel detector is adapted for the detection of short wavelength infrared radiation in the wavelength range of 1-1.6 μm.

### Claim 35 (depends on 33)

The system of claim 33, wherein the at least one silicon layer (127, 217, 417) of the readout wafer comprises an avalanche region.

### Claim 36 (depends on 34)

The system of claim 34, wherein the at least one silicon layer (127, 217, 417, 517) of the readout wafer comprises an avalanche region.

### Claim 37 (depends on 1)

A system for security applications comprising the pixel detector of claim 1.

### Claim 38 (depends on 37)

The system of claim 37, wherein the pixel detector is adapted for high spectral resolution for the detection and analysis of liquids in airplane luggage.

### Claim 39 (depends on 1)

A system for mammography applications comprising the pixel detector of claim 1.

### Claim 40 (depends on 39)

The system of claim 39, wherein the pixel detector is adapted for high spatial and spectral resolution at X-ray tube voltages operated below 40 keV to permit reliable identification of micro-calcification in women's breasts.

### Claim 41 (depends on 1)

A system for high resolution displays comprising the pixel detector of claim 1.

### Claim 42 (depends on 41)

The system of claim 41, wherein the absorber wafer is configured to act as an emitter wafer under bias conditions inverse to those of detector operations.

### Claim 43 (depends on 41)

The system of claim 41, wherein the pixel detector is configured to operate under bias conditions inverse to those of detector operation in order to act as a high resolution LED pixel array.

### Claim 44 (depends on 43)

The high resolution LED pixel array of claim 43, wherein the size of the LED pixels is a size selected from one of a list of sizes consisting of 80-100 μm, 60-80 μm, 40-60 μm, 20-40 μm and 10-20 μm.

### Claim 45 (depends on 42, 43, 44)

The system of one of claims 42-44, wherein the emitter wafer comprises a stack of semiconductor layers chosen from a list of semiconductor layers comprising at least GaN, GaAlN, AlGaInN and GaInN layers.