# US 2019/0172846 A1 · Method of forming an integrated circuit (ic) with shallow trench isolation (sti) regions and the resulting ic structure

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2019/0172846 A1
- Document ID: US20190172846A1
- Status: Published application
- Kind: A1
- Application number: 16/258,714
- Filed: 2019-01-28
- Published: 2019-06-06
- Earliest claimed: 2017-02-24
- Assignees: Globalfoundries Inc.
- Applicants: Globalfoundries Inc.
- Inventors: Anthony K. Stamper; Steven M. Shank; Siva P. Adusumilli
- Web page: https://patentgrep.com/patent/US20190172846A1

## CPC

- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 1/47: Resistors having no potential barriers
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties}
- H10D 86/01: Manufacture or treatment
- H10D 86/011: {comprising FinFETs}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 86/60: wherein the TFTs are in active matrices
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/8316: {the IGFETs characterised by having gate sidewall spacers specially adapted for integration}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 86/215: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed is an integrated circuit (IC) formation method, wherein trenches are formed within a semiconductor layer to define semiconductor mesa(s). Instead of immediately filling the trenches with an isolation material and performing a planarizing process to complete the STI regions prior to device formation, the method initially only form sidewall spacers within the trenches on the exposed sidewalls of the semiconductor mesa(s). After the sidewall spacers are formed, device(s) (e.g., field effect transistor(s), silicon resistor(s), etc.) are formed using the semiconductor mesa(s) and, optionally, additional device(s) (e.g., polysilicon resistor(s)) can be formed within the trenches between adjacent semiconductor mesas. Subsequently, middle of the line (MOL) dielectrics (e.g., a conformal etch stop layer and a blanket interlayer dielectric (ILD) layer) are deposited over the device(s), thereby filling any remaining space within the trenches and completing the STI regions. Also disclosed is an IC structure formed using the method.

## Claims

### Claim 1

An integrated circuit structure comprising:
trenches extending vertically through a semiconductor layer, the trenches defining at least one semiconductor mesa;
first sidewall spacers within the trenches positioned laterally adjacent to first sidewalls of the semiconductor mesa;
a device comprising the semiconductor mesa; and,
a blanket interlayer dielectric layer covering the device and within at least one of the trenches, wherein the first sidewall spacers and the blanket interlayer dielectric layer comprise different dielectric materials.

### Claim 2 (depends on 1)

The integrated circuit structure of claim 1, further comprising a conformal etch stop layer in at least some of the trenches and covering the device,
wherein the blanket interlayer dielectric layer is above and immediately adjacent to the conformal etch stop layer, and
wherein the conformal etch stop layer comprises a different dielectric material than the blanket interlayer dielectric layer.

### Claim 3 (depends on 1)

The integrated circuit structure of claim 1, wherein the device comprises any of a field effect transistor and a resistor.

### Claim 4 (depends on 1)

The integrated circuit structure of claim 1,
wherein the device comprises a field effect transistor comprising a gate on a top surface of the semiconductor mesa,
wherein the integrated circuit structure further comprises second sidewall spacers and third sidewall spacers,
wherein the second sidewall spacers are positioned laterally adjacent to second sidewalls of the gate,
wherein the third sidewall spacers are within the trenches positioned laterally adjacent to the first sidewall spacers, and
wherein the second sidewall spacers and the third sidewall spacers comprise a different dielectric material than the first sidewall spacers.

### Claim 5 (depends on 4)

The integrated circuit structure of claim 4, wherein the gate has a first portion above the top surface of the semiconductor mesa and a second portion within an adjacent trench.

### Claim 6 (depends on 1)

The integrated circuit structure of claim 1, further comprising a liner lining the trenches and an additional device within one of the trenches above the liner and positioned laterally between adjacent semiconductor mesas.

### Claim 7 (depends on 6)

The integrated circuit structure of claim 6, wherein the liner comprises an oxide liner, wherein the additional device comprises a polysilicon resistor, and wherein the integrated circuit structure further comprises a protective layer above and immediately adjacent to a top surface of the polysilicon resistor.

### Claim 8

An integrated circuit structure comprising:
trenches extending vertically through a semiconductor layer, the trenches defining multiple semiconductor mesas;
a liner lining the trenches;
first sidewall spacers within the trenches positioned laterally adjacent to first sidewalls of the semiconductor mesas, wherein the first sidewall spacers are physically separated from the first sidewalls by the liner;
multiple devices comprising at least:
a first semiconductor device comprising a first semiconductor mesa of the semiconductor mesas; and
a second semiconductor device comprising a second semiconductor mesa of the semiconductor mesas, wherein the first semiconductor device and the second semiconductor device comprise different types of semiconductor devices; and,
a blanket interlayer dielectric layer over the multiple devices and within at least one of the trenches, wherein the first sidewall spacers and the blanket interlayer dielectric layer comprise different dielectric materials.

### Claim 9 (depends on 8)

The integrated circuit structure of claim 8, wherein the first semiconductor device comprises a field effect transistor and the second semiconductor device comprises a resistor.

### Claim 10 (depends on 9)

The integrated circuit structure of claim 9,
wherein the field effect transistor comprises a channel region positioned laterally between source/drain regions within the first semiconductor mesa, a gate on a top surface of the first semiconductor mesa at the channel region and silicide layers on top surfaces of the gate and the first semiconductor mesa at the source/drain regions, and
wherein the integrated circuit structure further comprises:
a protective layer above and immediately adjacent to a top surface of the second semiconductor mesa; and
a conformal etch stop layer in at least some of the trenches and covering the multiple devices, wherein the conformal etch stop layer is above and immediately adjacent to the protective layer and further above and immediately adjacent to the silicide layers on the gate and the first semiconductor mesa.

### Claim 11 (depends on 10)

The integrated circuit structure of claim 10,
wherein the blanket interlayer dielectric layer is above and immediately adjacent to the conformal etch stop layer, and
wherein the conformal etch stop layer comprises a different dielectric material than the blanket interlayer dielectric layer.

### Claim 12 (depends on 10)

The integrated circuit structure of claim 10,
wherein the integrated circuit structure further comprises second sidewall spacers and third sidewall spacers,
wherein the second sidewall spacers are positioned laterally adjacent to second sidewalls of the gate,
wherein the third sidewall spacers are within the trenches positioned laterally adjacent to the first sidewall spacers, and
wherein the second sidewall spacers and the third sidewall spacers comprise a different dielectric material than the first sidewall spacer.

### Claim 13 (depends on 10)

The integrated circuit structure of claim 10, wherein the gate has a first portion above the top surface of the first semiconductor mesa at the channel region and a second portion within an adjacent trench.

### Claim 14 (depends on 10)

The integrated circuit structure of claim 10, the multiple devices further comprising a polysilicon resistor within one of the trenches above the liner and positioned laterally between adjacent semiconductor mesas, wherein the liner comprises an oxide liner, and wherein the protective layer is further above and immediately adjacent to the top surface of the polysilicon resistor.

### Claim 15

An integrated circuit structure comprising:
trenches extending vertically through a semiconductor layer, the trenches defining multiple semiconductor mesas;
an oxide liner lining the trenches;
first sidewall spacers within the trenches positioned laterally adjacent to first sidewalls of each of the semiconductor mesas, wherein the first sidewall spacers are physically separated from the first sidewalls by the oxide liner;
multiple devices comprising at least:
a first semiconductor device comprising a first semiconductor mesa of the semiconductor mesas; and
a second semiconductor device within one of the trenches above the oxide liner and positioned laterally between adjacent semiconductor mesas; and,
a blanket interlayer dielectric layer over the multiple devices and within at least one of the trenches, wherein the first sidewall spacers and the blanket interlayer dielectric layer comprise different dielectric materials.

### Claim 16 (depends on 15)

The integrated circuit structure of claim 15, wherein the first semiconductor device comprises a field effect transistor and the second semiconductor device comprises a polysilicon resistor.

### Claim 17 (depends on 16)

The integrated circuit structure of claim 16,
wherein the field effect transistor comprises a channel region positioned laterally between source/drain regions within the first semiconductor mesa, a gate on a top surface of the first semiconductor mesa at the channel region and silicide layers on top surfaces of the gate and the first semiconductor mesa at the source/drain regions, and
wherein the integrated circuit structure further comprises:
a protective layer above and immediately adjacent to a top surface of the polysilicon resistor; and
a conformal etch stop layer in at least some of the trenches and covering the multiple devices, wherein the conformal etch stop layer is above and immediately adjacent to the protective layer on the polysilicon resistor and further above and immediately adjacent to the silicide layers on the gate and the first semiconductor mesa.

### Claim 18 (depends on 17)

The integrated circuit structure of claim 17,
wherein the blanket interlayer dielectric layer is above and immediately adjacent to the conformal etch stop layer,
wherein the conformal etch stop layer comprises a different dielectric material than the blanket interlayer dielectric layer,
wherein the integrated circuit structure further comprises second sidewall spacers and third sidewall spacers,
wherein the second sidewall spacers are positioned laterally adjacent to second sidewalls of the gate,
wherein the third sidewall spacers are within the trenches positioned laterally adjacent to the first sidewall spacers, and
wherein the second sidewall spacers and the third sidewall spacers comprise a different dielectric material than the first sidewall spacer.

### Claim 19 (depends on 18)

The integrated circuit structure of claim 18, wherein the gate has a first portion above the top surface of the first semiconductor mesa and a second portion within an adjacent trench.

### Claim 20 (depends on 17)

The integrated circuit structure of claim 17, wherein the multiple devices further comprise a silicon resistor comprising a second semiconductor mesa of the semiconductor mesas, wherein the protective layer is further above and immediately adjacent to a top surface of the second semiconductor mesa.