# US 2019/0172841 A1 · Semiconductor integrated circuit device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0172841 A1 - Document ID: US20190172841A1 - Status: Published application - Kind: A1 - Application number: 16/269,360 - Filed: 2019-02-06 - Published: 2019-06-06 - Earliest claimed: 2016-08-08 - Assignees: Socionext Inc. - Applicants: Socionext Inc. - Inventors: Keisuke KISHISHITA - Web page: https://patentgrep.com/patent/US20190172841A1 ## CPC - H10D 84/907: {CMOS gate arrays} - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels - H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 62/10: Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies - H10D 84/83: of only insulated-gate FETs [IGFET] - H10D 84/8311: {the IGFETs characterised by having different channel structures} - H10D 84/85: Complementary IGFETs, e.g. CMOS - H10D 89/10: Integrated device layouts - H10D 62/121: {oriented parallel to substrates} - H10D 84/0128: {Manufacturing their channels} - H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes} - H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/912: {4-T CMOS basic cells} - H10D 84/935: {Degree of specialisation for implementing specific functions} - H10D 84/957: {SOS or SOI technology} - H10D 84/961: {Substrate and well contacts} - H10D 84/964: {Yield or reliability} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ## Abstract Provided is a semiconductor integrated circuit device including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the device easy. In a standard cell including nanowire FETs connected in series through an intermediate node used only for mutual connection, the nanowire FETs include first, second, and third pads, Na nanowires extending in an X direction between the first and second pads to connect the first and second pads together, and Nb nanowires extending in the X direction between the second and third pads to connect the second and third pads together. ## Claims ### Claim 1 A semiconductor integrated circuit, comprising: a standard cell including first and second transistors that are nanowire field effect transistors (FETs), the first and second transistors being connected in series through a connection node used only for mutual connection, wherein the first and second transistors include: a first pad; Na (Na is an integer of one or more) first nanowires each having a first end that is connected to the first pad, each extending in a first direction from the first end, and each having a lower surface above a lower surface of the first pad; a first gate electrode surrounding peripheries of the first nanowires within predetermined ranges of the first nanowires in the first direction; a second pad connected to second ends of the first nanowires; Nb (Nb is an integer of one or more) second nanowires each having a first end that is connected to the second pad, each extending in the first direction from the first end, and each having a lower surface above a lower surface of the second pad; a second gate electrode surrounding peripheries of the second nanowires within predetermined ranges of the second nanowires in the first direction; and a third pad connected to second ends of the second nanowires. ### Claim 2 (depends on 1) The semiconductor integrated circuit of claim 1, wherein in the standard cell, the first and second nanowires have the same length in the first direction. ### Claim 3 (depends on 1) The semiconductor integrated circuit of claim 1, wherein the first and second transistors are transistors of the same conductive type, and a same signal is input to gates of the first and second transistors. ### Claim 4 (depends on 1) The semiconductor integrated circuit of claim 1, wherein the standard cell is a NAND gate or a NOR gate, and the first and second transistors constitute a serial portion of the NAND gate or the NOR gate. ### Claim 5 (depends on 1) The semiconductor integrated circuit of claim 1, wherein the number (Na) of the first nanowires is greater than the number (Nb) of the second nanowires. ### Claim 6 (depends on 5) The semiconductor integrated circuit of claim 5, further comprising: a dummy gate electrode aligned with the second gate electrode while being separated from the second gate electrode. ### Claim 7 (depends on 6) The semiconductor integrated circuit of claim 6, wherein the second gate electrode is shorter than the first gate electrode. ### Claim 8 (depends on 5) The semiconductor integrated circuit of claim 5, wherein the standard cell includes a third transistor that is a dummy nanowire FET having no contribution to a logical operation of a circuit, and the third transistor includes: a dummy nanowire provided between the second pad and the third pad and extending in the first direction; and a dummy gate electrode aligned with the second gate electrode while being separated from the second gate electrode, and surrounding a periphery of the dummy nanowire within a predetermined range of the dummy nanowire in the first direction. ### Claim 9 (depends on 5) The semiconductor integrated circuit of claim 5, wherein the standard cell includes a third transistor that is a dummy nanowire FET having no contribution to a logical operation of a circuit, and the third transistor includes: a dummy nanowire provided so as to extend in the first direction in parallel with the second nanowires; and a dummy pad arranged together with the third pad, and separated from the third pad, in a second direction perpendicular to the first direction, having a lower surface below a lower surface of the dummy nanowire, and connected to the dummy nanowire. ### Claim 10 (depends on 9) The semiconductor integrated circuit of claim 9, further comprising: a dummy gate electrode aligned with the second gate electrode while being separated from the second gate electrode, and surrounding a periphery of the dummy nanowire within a predetermined range of the dummy nanowire in the first direction. ### Claim 11 A semiconductor integrated circuit, comprising: a standard cell including first and second transistors that are nanowire field effect transistors (FETs), wherein the first and second transistors include: a first pad; Na (Na is an integer of one or more) first nanowires each having a first end that is connected to the first pad, each extending in a first direction from the first end, and each having a lower surface above a lower surface of the first pad; a first gate electrode surrounding peripheries of the first nanowires within predetermined ranges of the first nanowires in the first direction; a second pad connected to second ends of the first nanowires; Nb (Nb is an integer of one or more) second nanowires each having a first end that is connected to the second pad, each extending in the first direction from the first end, and each having a lower surface above a lower surface of the second pad; a second gate electrode surrounding peripheries of the second nanowires within predetermined ranges of the second nanowires in the first direction; and a third pad connected to second ends of the second nanowires, and the second pad is not connected to any interconnect other than the first and second nanowires. ### Claim 12 (depends on 11) The semiconductor integrated circuit of claim 11, wherein in the standard cell, the first and second nanowires have the same length in the first direction. ### Claim 13 (depends on 11) The semiconductor integrated circuit of claim 11, wherein the first and second transistors are transistors of the same conductive type, and a same signal is input to gates of the first and second transistors. ### Claim 14 (depends on 11) The semiconductor integrated circuit of claim 11, wherein the standard cell is a NAND gate or a NOR gate, and the first and second transistors constitute a serial portion of the NAND gate or the NOR gate. ### Claim 15 (depends on 11) The semiconductor integrated circuit of claim 11, wherein the number (Na) of the first nanowires is greater than the number (Nb) of the second nanowires. ### Claim 16 A semiconductor integrated circuit, comprising: a standard cell that is a NAND gate or a NOR gate having a serial portion including M (M is an integer of two or more) nanowire field effect transistors (FETs), wherein the M nanowire FETs include: M+1 pads arranged at a predetermined pitch in a first direction; M groups of nanowires each including L (L is an integer of 1 or more) nanowires that are each provided between adjacent ones of the pads, extend in the first direction to connect the adjacent ones of the pads together, and each have a lower surface above lower surfaces of the pads; and M gate electrodes surrounding peripheries of the associated nanowires within predetermined ranges of the associated nanowires in the first direction. ### Claim 17 (depends on 16) The semiconductor integrated circuit of claim 16, wherein the M nanowires have the same length in the first direction.