# US 2019/0172840 A1 · Semiconductor device

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- Number: US 2019/0172840 A1
- Document ID: US20190172840A1
- Status: Published application
- Kind: A1
- Application number: 16/138,416
- Filed: 2018-09-21
- Published: 2019-06-06
- Earliest claimed: 2017-12-06
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Min Sung SONG; Heung Jin JOO; Kwan Yong KIM; Jin Woo PARK; Du Heon SONG; He Jueng LEE; Myung Ho JUNG
- Web page: https://patentgrep.com/patent/US20190172840A1

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/10: characterised by the top-view layout
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

In some embodiments, 3-dimensional semiconductor memory device includes a semiconductor substrate extending horizontally in a first direction and a second direction crossing the first direction. A stacked memory cell array is formed on the semiconductor substrate. The memory device further includes a separation pattern including a plurality of separation lines extending in the first direction and arranged in the second direction, and dividing the stacked memory cell array into a plurality of memory cell structures extending in the first direction and arranged in the second direction. An upper insulating layer is formed above the plurality of memory cell structures and separation lines, and a passivation layer is formed above the upper insulating layer. The passivation layer includes a plurality of first regions having a first vertical thickness. A plurality of gap regions in the passivation layer are formed between the plurality of first regions. The plurality of first regions vertically overlap the plurality of memory cell structures, and the plurality of gap regions vertically overlap the plurality of separation lines.

## Claims

### Claim 1

A 3-dimensional semiconductor memory device comprising:
a semiconductor substrate extending horizontally in a first direction and a second direction crossing the first direction;
a stacked memory cell array formed on the semiconductor substrate;
a separation pattern including a plurality of separation lines extending in the first direction and arranged in the second direction, and dividing the stacked memory cell array into a plurality of memory cell structures extending in the first direction and arranged in the second direction;
an upper insulating layer formed above the plurality of memory cell structures and separation lines; and
a passivation layer formed above the upper insulating layer, wherein:
the passivation layer includes a plurality of first regions having a first vertical thickness,
a plurality of gap regions in the passivation layer are formed between the plurality of first regions, and
the plurality of first regions vertically overlap the plurality of memory cell structures, and the plurality of gap regions vertically overlap the plurality of separation lines.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1, wherein:
the plurality of gap regions comprise a plurality of second regions of the passivation layer having a second vertical thickness different from the first vertical thickness.

### Claim 3 (depends on 2)

The semiconductor memory device of claim 2, wherein:
the stacked memory cell array is a vertical NAND memory cell array, and the plurality of memory cell structures are a plurality of gate stack structures each including a plurality of gate electrode layers alternately formed with a plurality of interlayer insulating layers on the substrate in a vertical stack.

### Claim 4 (depends on 2)

The semiconductor memory device of claim 2, wherein:
the first regions combined with the second regions are arranged to reduce warpage of the semiconductor memory device in the first direction and to reduce warpage of the semiconductor memory device in the second direction.

### Claim 5 (depends on 4)

The semiconductor memory device of claim 4, wherein:
the first regions combined with the second regions reduce warpage in the first direction by a greater amount than the first regions combined with the second regions reduce warpage in the second direction.

### Claim 6 (depends on 2)

The semiconductor memory device of claim 2, wherein:
the first vertical thickness is larger than the second vertical thickness.

### Claim 7

(canceled)

### Claim 8 (depends on 1)

The semiconductor memory device of claim 1, wherein:
the stacked memory cell array is a vertical NAND memory cell array, and the plurality of memory cell structures are a plurality of gate stack structures each including a plurality of gate electrode layers alternately formed with a plurality of interlayer insulating layers on the substrate in a vertical stack; and
the first regions combined with the gap regions are arranged to reduce warpage of the semiconductor memory device in the first direction and to reduce warpage of the semiconductor memory device in the second direction.

### Claim 9

(canceled)

### Claim 10

(canceled)

### Claim 11 (depends on 1)

The semiconductor memory device of claim 1, wherein:
the passivation layer includes:
a first surface that is continuous and that is flat or curved; and
a second surface opposite the first surface and that has a step shape.

### Claim 12

(canceled)

### Claim 13 (depends on 1)

The semiconductor memory device of claim 1, wherein:
the first regions are first line patterns extending in the first direction and having a first width in the second direction, and
the gap regions are second line patterns extending in the first direction that have a smaller vertical thickness than the first regions and that have a second width in the second direction, the second width being smaller than the first width.

### Claim at position 14

14-19. (canceled)

### Claim 20

A vertical NAND (VNAND) semiconductor device comprising:
a semiconductor substrate;
a plurality of gate electrode layers alternately formed with a plurality of interlayer insulating layers on the substrate in a vertical stack, and forming a plurality of gate stack structures extending in a first horizontal direction and separated from each other in a second horizontal direction perpendicular to the first direction;
a plurality of vertical channels passing through each of the plurality of gate stack structures, wherein the plurality of vertical channels form transistor strings;
a plurality of separation areas extending in the first horizontal direction and arranged in the second horizontal direction between the plurality of gate stack structures to separate the gate stack structures from each other;
an upper insulating layer formed above the plurality of gate electrode layers; and
a passivation layer formed above the upper insulating layer,
wherein:
the passivation layer includes a plurality of first regions having a first vertical thickness, and
a plurality of gap regions in the passivation layer are formed between the plurality of first regions, and
wherein the plurality of first regions vertically overlap the plurality of gate stack structures, and the plurality of gap regions vertically overlap the plurality of separation areas.

### Claim 21 (depends on 20)

The semiconductor device of claim 20, wherein:
the plurality of gap regions comprise a plurality of second regions of the passivation layer having a second vertical thickness different from the first vertical thickness.

### Claim 22 (depends on 21)

The semiconductor device of claim 21, wherein:
the first vertical thickness is larger than the second vertical thickness; and
a width in the second horizontal direction of each first region is larger than a width in the second horizontal direction of each of second region.

### Claim 23 (depends on 22)

The semiconductor device of claim 22, wherein:
a ratio of the first vertical thickness to the second vertical thickness is between 5:3 and 5:4.

### Claim at position 19

24-29. (canceled)

### Claim 30 (depends on 20)

The semiconductor device of claim 20, wherein:
the passivation layer includes:
a first surface that is continuous and that is flat or curved; and
a second surface opposite the first surface and that has a step shape.

### Claim at position 21

31-34. (canceled)

### Claim 35 (depends on 20)

The semiconductor device of claim 20, wherein:
the first regions are first line patterns extending in the first horizontal direction; and
the gap regions are second line patterns extending in the first horizontal direction and wider in the second horizontal direction than the first line patterns.

### Claim 36 (depends on 20)

The semiconductor device of claim 20, wherein:
the passivation layer is patterned to reduce the amount of warpage of the semiconductor device in the first horizontal direction while limiting the warpage of the semiconductor device in the second horizontal direction.

### Claim 37

(canceled)

### Claim 38

A vertical NAND (VNAND) semiconductor device comprising:
a semiconductor substrate;
a plurality of gate stack structures formed on the semiconductor substrate, the plurality of gate stack structures extending lengthwise in a first direction and separated from each other in a second direction perpendicular to the first direction;
a plurality of vertical channels passing through each of the plurality of gate stack structures, wherein the plurality of vertical channels form transistor strings;
a plurality of separation areas extending lengthwise in the first direction and arranged in the second direction between the plurality of gate stack structures to separate the gate stack structures from each other;
an upper insulating layer formed above the plurality of gate stack structures; and
a passivation layer formed above the upper insulating layer,
wherein the passivation layer includes a plurality of first line patterns extending in the first direction and having a first vertical thickness and includes a plurality of second line patterns having a second vertical thickness smaller than the first vertical thickness and extending in the first direction, and
wherein the first line patterns are arranged to reduce warpage of the semiconductor device in the first direction and the first line patterns combined with the second line patterns are arranged to reduce warpage of the semiconductor device in the second direction.

### Claim 39 (depends on 38)

The semiconductor device of claim 38, wherein:
the plurality of first line patterns are vertically aligned with the plurality of gate stack structures, and
the plurality of second line patterns are vertically aligned with the plurality of separation areas.

### Claim 40 (depends on 38)

The semiconductor device of claim 38, wherein:
the passivation layer includes:
a first surface that is continuous and is flat or curved, and
a second surface opposite the first surface and that has a step shape.

### Claim 41 (depends on 38)

The semiconductor device of claim 38, wherein:
the first line patterns reduce warpage in the first direction by a greater amount than the first line patterns combined with the second line patterns reduce warpage in the second direction.

### Claim at position 29

42-51. (canceled)