# US 2019/0172838 A1 · Three-dimensional semiconductor memory devices

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- Number: US 2019/0172838 A1
- Document ID: US20190172838A1
- Status: Published application
- Kind: A1
- Application number: 16/108,294
- Filed: 2018-08-22
- Published: 2019-06-06
- Earliest claimed: 2017-12-01
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Kwonsoon Jo; Seo-Goo Kang; Younghwan Son; Kohji Kanamori
- Web page: https://patentgrep.com/patent/US20190172838A1

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- G11C 7/14: Dummy cell management; Sense reference voltage generators
- G11C 7/18: Bit line organisation; Bit line lay-out
- G11C 16/00: Erasable programmable read-only memories (G11C14/00 takes precedence)
- H10B 43/10: characterised by the top-view layout
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 20/48: Insulating materials thereof
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A three-dimensional semiconductor memory device includes a peripheral logic structure including a plurality of peripheral logic circuits disposed on a semiconductor substrate, a horizontal semiconductor layer disposed on the peripheral logic structure, an electrode structure including a plurality of electrodes and insulating layers vertically and alternately stacked on the horizontal semiconductor layer, and a through-interconnection structure penetrating the electrode structure and the horizontal semiconductor layer and including a through-plug connected to the peripheral logic structure. A sidewall of a first insulating layer of the insulating layers is spaced apart from the through-plug by a first distance. A sidewall of a first electrode of the electrodes is spaced apart from the through-plug by a second distance greater than the first distance.

## Claims

### Claim 1

A three-dimensional (3D) semiconductor memory device comprising:
a peripheral logic structure comprising a plurality of peripheral logic circuits disposed on a semiconductor substrate;
a horizontal semiconductor layer disposed on the peripheral logic structure;
an electrode structure comprising a plurality of electrodes and insulating layers vertically and alternately stacked on the horizontal semiconductor layer; and
a through-interconnection structure penetrating the electrode structure and the horizontal semiconductor layer and comprising a through-plug connected to the peripheral logic structure,
wherein a sidewall of a first insulating layer of the insulating layers is spaced apart from the through-plug by a first distance, and
wherein a sidewall of a first electrode of the electrodes is spaced apart from the through-plug by a second distance greater than the first distance.

### Claim 2 (depends on 1)

The 3D semiconductor memory device of claim 1, wherein a sidewall of the horizontal semiconductor layer is spaced apart from the through-plug by a third distance, and the third distance is greater than a minimum distance between a sidewall of the electrode structure and the through-plug.

### Claim 3 (depends on 2)

The 3D semiconductor memory device of claim 2, wherein the third distance between the sidewall of the horizontal semiconductor layer and the through-plug is different from the second distance.

### Claim 4 (depends on 1)

The 3D semiconductor memory device of claim 1, wherein the horizontal semiconductor layer is closer to the first electrode than the first insulating layer.

### Claim 5 (depends on 1)

The 3D semiconductor memory device of claim 1, wherein a distance between the through-plug and a second insulating layer corresponding to an uppermost one of the insulating layers is greater than the first distance.

### Claim 6 (depends on 1)

The 3D semiconductor memory device of claim 1, wherein distances between the through-plug and sidewalls of the electrodes increase as a vertical distance from the horizontal semiconductor layer to each of the electrodes increases.

### Claim 7 (depends on 1)

The 3D semiconductor memory device of claim 1, wherein distances between the through-plug and sidewalls of the insulating layers increase as a vertical distance from the horizontal semiconductor layer to each of the insulating layers increases.

### Claim 8 (depends on 1)

The 3D semiconductor memory device of claim 1, wherein the through-interconnection structure further comprises a through-insulating, pattern surrounding the through-plug, and
wherein the through-insulating pattern comprises protrusions that laterally protrude toward the electrodes and are provided between the insulating layers.

### Claim 9 (depends on 8)

The 3D semiconductor memory device of claim 8, wherein a bottom width of a bottom surface of the through-insulating, pattern is less than a top width of a top surface of the through-insulating pattern.

### Claim 10 (depends on 8)

The 3D semiconductor memory device of claim 8, wherein the insulating layers of the electrode structure include a first insulating material, and
wherein the through-insulating pattern includes a second insulating material different from the first insulating material.

### Claim 11 (depends on 1)

The 3D semiconductor memory device of claim 1, wherein the horizontal semiconductor layer includes a cell array region and a connection region,
wherein the electrode structure extends from the cell array region onto the connection region and has a stepped structure on the connection region, and
wherein the through-interconnection structure is spaced apart from the stepped structure of the electrode structure.

### Claim 12 (depends on 11)

The 3D semiconductor memory device of claim 11, further comprising:
cell vertical structures penetrating the electrode structure on the cell array region; and
dummy vertical structures penetrating the stepped structure of the electrode structure on the connection region,
wherein each of the cell and dummy vertical structures comprises:
a semiconductor pattern connected to the horizontal semiconductor layer; and
a data storage pattern surrounding a sidewall of the semiconductor pattern.

### Claim 13 (depends on 1)

The 3D semiconductor memory device of claim 1, further comprising:
contact plugs connected to the electrodes of the electrode structure; and
a conductive line connecting the through-plug to one of the contact plugs.

### Claim 14

A three-dimensional (3D) semiconductor memory device comprising:
a peripheral logic structure comprising a plurality of peripheral logic circuits disposed on a semiconductor substrate;
a horizontal semiconductor layer disposed on the peripheral logic structure;
an electrode structure comprising a plurality of electrodes and insulating layers which are vertically and alternately stacked on the horizontal semiconductor layer, the electrode structure having a plurality of recess regions between the insulating layers vertically adjacent to each other;
a through-insulating pattern penetrating a portion of the electrode structure and a portion of the horizontal semiconductor layer and filling the recess regions of the electrode structure; and
a plurality of through-plugs penetrating the through-insulating pattern and connected to the peripheral logic structure.

### Claim 15 (depends on 14)

The 3D semiconductor memory device of claim 14, wherein a sidewall of the horizontal semiconductor layer is spaced apart from a first through-plug of the through-plugs by a first distance, and
wherein a sidewall of a lowermost electrode of the electrodes is spaced apart from the first through-plug by a second distance different from the first distance.

### Claim 16 (depends on 15)

The 3D semiconductor memory device of claim 15, wherein the first distance is greater than a minimum distance between the first through-plug and a sidewall of the electrode structure, which has the recess regions.

### Claim 17 (depends on 14)

The 3D semiconductor memory device of claim 14, wherein the insulating layers of the electrode structure include a first insulating material, and
wherein the through-insulating pattern includes a second insulating material different from the first insulating material.

### Claim 18 (depends on 14)

The 3D semiconductor memory device of claim 14, wherein a bottom width of a bottom surface of the through-insulating pattern is less than a top width of a top surface of the through-insulating pattern.

### Claim 19 (depends on 14)

The 3D semiconductor memory device of claim 14, wherein distances between the through-plugs and the recessed sidewalls of the electrodes increase as a vertical distance from the horizontal semiconductor layer to each of the electrodes increases.

### Claim 20

A three-dimensional (3D) semiconductor memory device comprising:
a peripheral logic structure comprising a plurality of peripheral logic circuits disposed on a semiconductor substrate;
a horizontal semiconductor layer disposed on the peripheral logic structure,
an electrode structure comprising a plurality of electrodes and insulating layers vertically and alternately stacked on the horizontal semiconductor layer; and
a through-interconnection structure penetrating the electrode structure and the horizontal semiconductor layer and comprising, a through-plug connected to the peripheral logic structure,
wherein the through-plug is spaced apart from a sidewall of the horizontal semiconductor layer by a first distance, and the first distance is greater than a minimum distance between a sidewall of the electrode structure and the through-plug.

### Claim at position 21

21-28. (canceled)