# US 2019/0172837 A1 · Semiconductor device

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- Number: US 2019/0172837 A1
- Document ID: US20190172837A1
- Status: Published application
- Kind: A1
- Application number: 16/269,797
- Filed: 2019-02-07
- Published: 2019-06-06
- Earliest claimed: 2017-04-28
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Tomohiro YAMASHITA; Tamotsu OGATA; Masamichi FUJITO; Tomoya SAITO
- Web page: https://patentgrep.com/patent/US20190172837A1

## CPC

- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/30: characterised by the memory core region
- H10B 43/35: with cell select transistors, e.g. NAND
- H10D 1/042: {using deposition processes to form electrode extensions}
- H10D 1/047: {of conductor-insulator-semiconductor capacitors, e.g. trench capacitors}
- H10D 1/66: Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
- H10D 1/714: {having horizontal extensions}
- H10D 1/716: {having vertical extensions}
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

To downsize a semiconductor device that includes a non-volatile memory and a capacitive element on a semiconductor substrate. In a capacitive element region of a main surface of a semiconductor substrate, fins protruding from the main surface are arranged along the Y direction while extending in the X direction. In the capacitive element region of the main surface of the semiconductor substrate, capacitor electrodes of the capacitive elements are alternately arranged along the X direction while intersecting the fins. The fins are formed in a formation step of other fins which are arranged in a memory cell array of the non-volatile memory of the semiconductor substrate. One capacitor electrode is formed in a formation step of a control gate electrode of the non-volatile memory. Another capacitor electrode is formed in a formation step of a memory gate electrode of the non-volatile memory.

## Claims

### Claim at position 1

1-20. (canceled)

### Claim 21

A method of manufacturing a semiconductor device, comprising the steps of:
(a) forming a plurality of first insulating films on a semiconductor substrate in a memory region and forming a plurality of second insulating films on the semiconductor substrate in a capacitive element region,
(b) performing an etching to the semiconductor substrate in a state that the first insulating films and the second insulating films are formed, thereby forming a plurality of first protrusions in the memory region and a plurality of second protrusions in the capacitive element region,
(c) forming a first conductive film via a third insulating film on the first protrusions and on the second protrusions,
(d) forming a plurality of control gate electrodes on the first protrusions and a plurality of first capacitor electrodes on the second protrusions by etching the first conductive film,
(e) forming a second conductive film via a fourth insulating film on the first protrusions and on the second protrusions so as to cover the control gate electrodes and the first capacitor electrodes,
(f) polishing the second conductive film and lowering an upper surface of the second conductive film, and
(g) removing a part of the second conductive film in the memory region, thereby forming a plurality of memory gate electrodes in the memory region such that each of the memory gate electrodes is adjacent to each of the control gate electrodes, and a plurality of second capacitor electrodes in the capacitive element region,
wherein a distance between the adjacent first protrusions is larger than a distance between the adjacent second protrusions.

### Claim 22 (depends on 21)

The method according to claim 21,
wherein a distance between the adjacent first insulating films is larger than a distance between the adjacent second insulating films.

### Claim 23 (depends on 21)

The method according to claim 21,
wherein the distance between the second protrusions is three times or more a thickness of the fourth insulating film.

### Claim 24 (depends on 21)

The method according to claim 21,
wherein each of the first protrusions has a width in a first direction along the semiconductor substrate and extends in a second direction along the semiconductor substrate and the first protrusions are arranged in the first direction, and
wherein each of the second protrusions has a width in the first direction and extends in the second direction and the second protrusions are arranged in the first direction.

### Claim 25 (depends on 21)

The method according to claim 21,
wherein a distance between the adjacent first capacitor electrodes is smaller than a distance between the adjacent control gate electrodes.

### Claim 26 (depends on 25)

The method according to claim 25,
wherein a distance between the adjacent first capacitor electrodes is three times or more a thickness of the fourth insulating film.

### Claim 27 (depends on 24)

The method according to claim 24,
wherein a width of the first capacitor electrode in the second direction is smaller than a width of the control gate electrode in the second direction.

### Claim 28 (depends on 21)

The method according to claim 21,
wherein the first protrusion, the control gate electrode and the memory gate electrode configure a memory cell, and
wherein the second protrusion, the first capacitor electrode and the second capacitor electrode configure a capacitor element.

### Claim 29 (depends on 21)

The method according to claim 21, further comprising the steps of:
(h) after the step (b), before the step (c), forming an isolation portion between the adjacent first protrusions and between the adjacent second protrusions,
(i) after the step (d), before the step (e), forming a resist film covering the memory cell region and exposing the isolation film between the adjacent first capacitor electrodes, and
(j) after the step (i), before the step (e), removing a part of the isolation film exposed from the resist film, and exposing a part of the semiconductor substrate between the adjacent first capacitor electrodes,
wherein, in a third direction orthogonal to a main surface of the semiconductor substrate, a length of the second capacitor electrode arranged between the adjacent second protrusions is larger than a length of the memory gate electrode arranged between the adjacent first protrusions.