# US 2019/0172823 A1 · Placement methodology to remove filler

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- Number: US 2019/0172823 A1
- Document ID: US20190172823A1
- Status: Published application
- Kind: A1
- Application number: 15/831,991
- Filed: 2017-12-05
- Published: 2019-06-06
- Earliest claimed: 2017-12-05
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Xiangdong Chen; Sorin Adrian Dobre; Hyeokjin Lim; Venugopal Boynapalli
- Web page: https://patentgrep.com/patent/US20190172823A1

## CPC

- H10D 89/10: Integrated device layouts
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10D 84/907: {CMOS gate arrays}
- H10D 84/974: {Layout specifications, i.e. inner core regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

In certain aspects, a semiconductor die includes a first cell and a second cell. The first cell includes first transistors, and a first interconnect structure interconnecting the first transistors to form a first circuit. The second cell includes second transistors, and a second interconnect structure interconnecting the second transistors to form a second circuit. The first circuit and the second circuit are configured to perform a same function, and a length of the first cell in a first lateral direction is greater than a length of the second cell in the first lateral direction.

## Claims

### Claim 1

A semiconductor die, comprising:
a first cell comprising:
first transistors; and
a first interconnect structure interconnecting the first transistors to form a first circuit; and
a second cell comprising:
second transistors; and
a second interconnect structure interconnecting the second transistors to form a second circuit;
wherein the first circuit and the second circuit are configured to perform a same function, and a length of the first cell in a first lateral direction is greater than a length of the second cell in the first lateral direction.

### Claim 2 (depends on 1)

The semiconductor die of claim 1, wherein a length of the first cell in a second lateral direction is approximately the same as a length of the second cell in the second lateral direction, and the second lateral direction is approximately perpendicular to the first lateral direction.

### Claim 3 (depends on 1)

The semiconductor die of claim 1, wherein:
the first cell comprises first gates, wherein the first transistors include at least a portion of one or more of the first gates; and
the second cell comprises second gates, wherein the second transistors include at least a portion of one or more of the second gates, and a number of the first gates is greater than a number of the second gates.

### Claim 4 (depends on 3)

The semiconductor die of claim 3, wherein the first gates are approximately spaced apart from one another by a gate pitch, the second gates are approximately spaced apart from one another by the gate pitch, and the length of the first cell in the first lateral direction is greater than the length of the second cell in the first lateral direction by at least the gate pitch.

### Claim 5 (depends on 4)

The semiconductor die of claim 4, wherein the first gates run parallel with one another along a second lateral direction, the second gates run parallel with one another along the second lateral direction, and the second lateral direction is approximately perpendicular to the first lateral direction.

### Claim 6 (depends on 5)

The semiconductor die of claim 5, wherein a length of the first cell in the second lateral direction is approximately the same as a length of the second cell in the second lateral direction.

### Claim 7 (depends on 3)

The semiconductor die of claim 3, wherein:
the first cell comprises a first active region, wherein the first transistors include at least a portion of the first active region; and
the second cell comprises a second active region, wherein the second transistors include at least a portion of the second active region, and a length of the first active region in the first lateral direction is greater than a length of the second active region in the first lateral direction.

### Claim 8 (depends on 7)

The semiconductor die of claim 7, wherein the first active region extends under the one or more of the first gates, and the second active region extends under the one or more of the second gates.

### Claim 9 (depends on 7)

The semiconductor die of claim 7, wherein the first gates are approximately spaced apart from one another by a gate pitch, the second gates are approximately spaced apart from one another by the gate pitch, and the length of the first active region in the first lateral direction is greater than the length of the second active region in the first lateral direction by at least the gate pitch.

### Claim 10 (depends on 7)

The semiconductor die of claim 7, wherein:
the first active region comprises first fins, wherein the first fins extend in the first lateral direction; and
the second active region comprises second fins, wherein the second fins extend in the first lateral direction.

### Claim 11 (depends on 1)

The semiconductor die of claim 1, wherein
the first interconnect structure includes a first input metal line and a first output metal line; and
the second interconnect structure interconnecting includes a second input metal and a second output metal line;
wherein a spacing between the first input metal line and the first output metal line is approximately the same as a spacing between the second input line and the second output metal line.

### Claim 12 (depends on 1)

The semiconductor die of claim 1, wherein each of the first and second circuits comprises a respective inverter.

### Claim 13 (depends on 12)

The semiconductor die of claim 12, wherein:
the first transistors comprise a first p-type field effect transistor (PFET) and a first n-type field effect transistor (NFET); and
the second transistors comprise a second PFET and a second NFET.

### Claim 14 (depends on 13)

The semiconductor die of claim 13, wherein:
the first interconnect structure couples a gate of the first PFET and a gate of the first NFET together, and couples a drain of the first PFET and a drain of the first NFET together; and
the second interconnect structure couples a gate of the second PFET and a gate of the second NFET together, and couples a drain of the second PFET and a drain of the second NFET together.

### Claim at position 15

15-20. (canceled)