# US 2019/0172794 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0172794 A1 - Document ID: US20190172794A1 - Status: Published application - Kind: A1 - Application number: 15/984,548 - Filed: 2018-05-21 - Published: 2019-06-06 - Earliest claimed: 2017-12-05 - Assignees: Toshiba Memory Corporation - Applicants: Toshiba Memory Corporation - Inventors: Sachiyo ITO; Tatsuhiro ODA - Web page: https://patentgrep.com/patent/US20190172794A1 ## CPC - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/30: characterised by the memory core region - H10B 43/10: characterised by the top-view layout - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/30: characterised by the memory core region - H10B 43/35: with cell select transistors, e.g. NAND - H10B 43/40: characterised by the peripheral circuit region - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10W 20/021: {of interconnections within wafers or substrates} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations} - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES ## Abstract According to one embodiment, a semiconductor device includes a substrate, a stacked body, a plurality of columnar portions, a separation portion, and a wall portion. The separation portion extends through the stacked body in a first direction and separates the stacked body into a plurality of blocks in a second direction. The separation portion includes a conductive material contacting the substrate. The wall portion is disposed between the separation portion and a columnar portion of the plurality of columnar portions most proximal to the separation portion. The wall portion pierces a lowermost electrode layer of the plurality of electrode layers and pierces an interface between the substrate and the stacked body. ## Claims ### Claim 1 A semiconductor device, comprising: a substrate; a stacked body provided above the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed; a plurality of columnar portions extending through the stacked body in a stacking direction of the stacked body; a separation portion extending through the stacked body in a first direction and separating the stacked body into a plurality of blocks in a second direction, the second direction crossing the first direction, the separation portion including a conductive material contacting the substrate; a wall portion disposed between the separation portion and a columnar portion of the plurality of columnar portions most proximal to the separation portion, the wall portion piercing a lowermost electrode layer of the plurality of electrode layers and piercing an interface between the substrate and the stacked body. ### Claim 2 (depends on 1) The device according to claim 1, wherein the substrate includes a plurality of protrusions piercing the lowermost electrode layer, and the columnar portions are provided on the protrusions. ### Claim 3 (depends on 1) The device according to claim 1, wherein the columnar portions include a plurality of semiconductor bodies extending through the stacked body in the stacking direction and contacting the substrate. ### Claim 4 (depends on 3) The device according to claim 3, wherein a charge storage portion is provided between one of the semiconductor bodies and one of the electrode layers. ### Claim 5 (depends on 2) The device according to claim 2, wherein the columnar portions include a plurality of semiconductor bodies extending through the stacked body in the stacking direction and contacting the protrusions. ### Claim 6 (depends on 5) The device according to claim 5, wherein a charge storage portion is provided between one of the semiconductor bodies and one of the electrode layers. ### Claim 7 (depends on 1) The device according to claim 1, wherein the wall portion includes an insulating film provided in at least a portion adjacent to the lowermost electrode layer. ### Claim 8 (depends on 1) The device according to claim 1, wherein a plurality of the wall portions is arranged in the first direction to be separated from each other. ### Claim 9 (depends on 8) The device according to claim 8, wherein a spacing between the wall portions adjacent to each other in the first direction is less than a length in the first direction of one of the wall portions. ### Claim 10 (depends on 1) The device according to claim 1, wherein a lower end of the wall portion is positioned higher than a lower end of the conductive material. ### Claim 11 (depends on 1) The device according to claim 1, wherein the conductive material includes silicon. ### Claim 12 (depends on 1) The device according to claim 1, wherein the conductive material includes a metal. ### Claim 13 (depends on 1) The device according to claim 1, wherein the separation portion includes an insulating film provided between the conductive material and the stacked body. ### Claim 14 (depends on 1) The device according to claim 1, further comprising a source line provided above the stacked body and electrically connected to an upper end of the conductive material. ### Claim 15 (depends on 1) The device according to claim 1, wherein the wall portion pierces lower electrode layers including the lowermost electrode layer, the wall portion not piercing upper electrode layers other than the lower electrode layers. ### Claim 16 A method for manufacturing a semiconductor device, comprising: forming a stacked body above a substrate, the stacked body including a plurality of first layers and a plurality of second layers, the first layers and the second layers including a first layer and a second layer stacked alternately; forming a wall portion piercing a lowermost first layer of the plurality of first layers and piercing an interface between the substrate and the stacked body; forming a plurality of columnar portions inside a plurality of holes, the holes piercing the stacked body and reaching the substrate; and forming a conductive material contacting the substrate inside a first slit, the first slit extending through the stacked body in a first direction and separating the stacked body into a plurality of blocks in a second direction crossing the first direction, the wall portion being located between the conductive material and a columnar portion of the plurality of columnar portions most proximal to the conductive material. ### Claim 17 (depends on 16) The method according to claim 16, further comprising forming a plurality of protrusions at bottoms of the holes by causing a material of the substrate to grow, the columnar portions being formed on the protrusions. ### Claim 18 (depends on 16) The method according to claim 16, wherein the forming of the stacked body includes forming a lower layer portion above the substrate and stacking an upper layer portion on the lower layer portion, the lower layer portion including at least the lowermost first layer, and the forming of the wall portion includes forming an insulating film inside a second slit before the stacking of the upper layer portion, the second slit extending in the first direction, piercing the lower layer portion, and reaching the substrate. ### Claim 19 (depends on 16) The method according to claim 16, wherein the first slit and the conductive material are formed after the forming of the columnar portions and the wall portion, and the columnar portions are formed after the forming of the wall portion. ### Claim 20 (depends on 16) The method according to claim 16, further comprising replacing the plurality of first layers with a plurality of electrode layers through the first slit.