# US 2019/0172789 A1 · Soi wafers with buried dielectric layers to prevent cu diffusion

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- Number: US 2019/0172789 A1
- Document ID: US20190172789A1
- Status: Published application
- Kind: A1
- Application number: 16/266,196
- Filed: 2019-02-04
- Published: 2019-06-06
- Earliest claimed: 2015-12-29
- Assignees: Globalfoundries Inc.
- Applicants: Globalfoundries Inc.
- Inventors: Anthony K Stamper; Mukta G. Farooq; John A Fitzsimmons
- Web page: https://patentgrep.com/patent/US20190172789A1

## CPC

- H10W 20/425: {Barrier, adhesion or liner layers}
- H10P 90/1914: {using bonding}
- H10P 90/1916: {with separation or delamination along an ion implanted layer, e.g. Smart-cut}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/039: {also covering sidewalls of the conductive structures}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2125: {Top-view shapes}
- H10W 20/218: {in silicon-on-insulator [SOI] wafers}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9226: {with via interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the second wafer includes a nitride layer. The nitride layer can be formed between the semiconductor substrate and the second oxide layer. A third oxide layer can be formed on the semiconductor substrate and the nitride layer is formed between the second oxide layer and the third oxide layer. The nitride layer can be formed between the active semiconductor layer and the first oxide layer. The first wafer can include a third oxide layer formed on the active semiconductor layer and the nitride layer is formed between the third oxide layer and the first oxide layer.

## Claims

### Claim 1

A semiconductor-on-insulator (SOI) semiconductor device, comprising:
an active semiconductor layer;
a buried insulator layer bonded on a first side thereof to the active semiconductor layer;
a substrate bonded to the buried insulator layer on a second side of the buried insulator layer,
wherein the buried insulator layer includes:
a pair of oxide layers including a first oxide layer bonded to an immediately adjacent second oxide layer, and
a nitride layer positioned between the pair of oxide layers and a selected one of the active semiconductor layer or the substrate.

### Claim 2 (depends on 1)

The SOI semiconductor device of claim 1, further comprising a third oxide layer positioned between the selected one of the active semiconductor layer or the substrate and the nitride layer.