# US 2019/0172784 A1 · Multi terminal capacitor within input output path of semiconductor package interconnect > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2019/0172784 A1 - Document ID: US20190172784A1 - Status: Published application - Kind: A1 - Application number: 16/269,730 - Filed: 2019-02-07 - Published: 2019-06-06 - Earliest claimed: 2016-07-11 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Charles L. Arvin; Jean Audet; Brian W. Quinlan; Charles L. Reynolds; Brian R. Sundlof - Web page: https://patentgrep.com/patent/US20190172784A1 ## CPC - H10W 20/496: {Capacitor integral with wiring layers} - H05K 1/0231: {Capacitors or dielectric substances} - H10W 70/685: comprising multiple insulating layers - H10W 70/69: Insulating materials thereof - H10W 72/00: Interconnections or connectors in packages - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/50: Bond wires - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H05K 2201/10015: Non-printed capacitor - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 72/07236: {Soldering or alloying} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/354: {comprising polymers} - H10W 72/877: {Bump connectors and die-attach connectors} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/00: Package configurations - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/728: {between a chip and a stacked discrete passive device, e.g. resistors, capacitors or inductors} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract An integrated circuit (IC) device, e.g., wafer, chip, die, interposer, carrier, etc., includes a patterned mask that includes a first opening that exposes a signal region of a first contact. The mask further includes a second opening that exposes a signal region of a second contact that neighbors the first contact. The mask further includes a first capacitor tab opening that extends from the first opening toward the second contact and further exposes an extension region of the first contact. The mask further includes a second capacitor tab opening that extends from the second opening toward the first contact and further exposes an extension region of the second contact. A multi terminal capacitor may be connected to the IC device such that a first terminal is connected to the extension region of the first contact and a second terminal is connected to the extension region of the second contact. ## Claims ### Claim 1 An integrated circuit (IC) device comprising: a first contact that neighbors a second contact; a patterned mask upon the IC device, the patterned mask comprising a first opening that exposes a signal region of the first contact and a second opening that exposes a signal region of the second contact; the patterned mask further comprising a first capacitor tab opening that extends from the first opening toward the second contact and further exposes an extension region of the first contact; and the patterned mask further comprising a second capacitor tab opening that extends from the second opening toward the first contact and further exposes an extension region of the second contact. ### Claim 2 (depends on 1) The IC device of claim 1, wherein the first capacitor tab opening is aligned with the second capacitor tab opening. ### Claim 3 (depends on 1) The IC device of claim 1, further comprising: a multi terminal capacitor comprising a first terminal directly connected to the extension region of the first contact and a second terminal directly connected to the extension region of the second contact. ### Claim 4 (depends on 3) The IC device of claim 3, wherein the patterned mask further comprises a mask portion between the neighboring first contact and the second contact. ### Claim 5 (depends on 4) The IC device of claim 4, wherein the mask portion between the neighboring first contact and the second contact comprises a surface facing the multi terminal capacitor that is closer to the IC device relative to a major top surface of the mask. ### Claim 6 (depends on 4) The IC device of claim 4, further comprising adhesive directly upon the mask portion, the adhesive connecting the multi terminal capacitor with the mask portion between the neighboring first contact and the second contact. ### Claim 7 (depends on 3) The IC device of claim 3, further comprising a first solder interconnect that contacts at least the signal region of a first contact and a second solder interconnect that contacts at least the signal region of a second contact. ### Claim 8 (depends on 7) The IC device of claim 7, wherein the first solder interconnect further connects the first terminal to the extension region of the first contact and wherein the second solder interconnect further connects the second terminal to the extension region of the second contact. ### Claim 9 (depends on 8) The IC device of claim 8, wherein there no inductance between the first solder interconnect and the first terminal and wherein there no inductance between the first solder interconnect and the extension region of the first contact. ### Claim 10 (depends on 9) The IC device of claim 9, wherein there no inductance between the second solder interconnect and the second terminal and wherein there no inductance between the second solder interconnect and the extension region of the second contact. ### Claim 11 An integrated circuit (IC) device fabrication method comprising: patterning a mask that is upon the IC device to form a first opening that exposes a signal region of a first contact, to form a second opening that exposes a signal region of a second contact that neighbors the first contact, to form a first capacitor tab opening that extends from the first opening toward the second contact and further exposes an extension region of the first contact, and to form a second capacitor tab opening that extends from the second opening toward the first contact and further exposes an extension region of the second contact. ### Claim 12 (depends on 11) The IC device fabrication method of claim 11, wherein the first capacitor tab opening is aligned with the second capacitor tab opening. ### Claim 13 (depends on 11) The IC device fabrication method of claim 11, further comprising: connecting a first terminal of a multi terminal capacitor to the extension region of the first contact; and connecting a second terminal of the multi terminal capacitor to the extension region of the second contact. ### Claim 14 (depends on 13) The IC device fabrication method of claim 13, wherein the mask is patterned further to retain a mask portion between the neighboring first contact and the second contact. ### Claim 15 (depends on 14) The IC device fabrication method of claim 14, wherein the mask portion between the neighboring first contact and the second contact comprises a surface facing the multi terminal capacitor that is closer to the IC device relative to a major top surface of the mask. ### Claim 16 (depends on 14) The IC device fabrication method of claim 14, further comprising: forming an adhesive upon the mask portion; and connecting the multi terminal capacitor and the mask portion with the adhesive between the neighboring first contact and the second contact. ### Claim 17 (depends on 13) The IC device fabrication method of claim 13, further comprising: forming a first solder interconnect upon at least the signal region of a first contact; and forming a second solder interconnect upon at least the signal region of a second contact. ### Claim 18 (depends on 17) The IC device fabrication method of claim 17, further comprising: reflowing the first solder interconnect to connect the first terminal to the extension region of the first contact; and reflowing the second solder interconnect to connect the second terminal to the extension region of the second contact. ### Claim 19 (depends on 18) The IC device fabrication method of claim 18, wherein there no inductance between the first solder interconnect and the first terminal and wherein there no inductance between the extension region of the first solder interconnect and the first contact. ### Claim 20 (depends on 19) The IC device fabrication method of claim 19, wherein there no inductance between the second solder interconnect and the second terminal and wherein there no inductance between the second solder interconnect and the extension region of the second contact.